tty: serial: OMAP: ensure FIFO levels are set correctly in non-DMA mode
Ensure FIFO levels are set correctly in non-DMA mode (the default). This patch will cause a receive FIFO threshold interrupt to be raised when there is at least one byte in the RX FIFO. It will also cause a transmit FIFO threshold interrupt when there is only one byte remaining in the TX FIFO. These changes fix the receive interrupt problem and part of the transmit interrupt problem. A separate set of issues must be worked around for the transmit path to have a basic level of functionality; a subsequent patch will address these. DMA operation is unaffected by this patch. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Govindraj Raja <govindraj.r@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Родитель
b5148856a2
Коммит
0a697b2225
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@ -46,6 +46,18 @@
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#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
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/* SCR register bitmasks */
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#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
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#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
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/* FCR register bitmasks */
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#define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
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#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
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#define OMAP_UART_FCR_TX_FIFO_TRIG_SHIFT 4
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/* TLR register bitmasks */
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#define OMAP_UART_TLR_TX_FIFO_TRIG_DMA_SHIFT 0
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static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
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/* Forward declaration of functions */
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@ -694,6 +706,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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unsigned char efr = 0;
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unsigned long flags = 0;
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unsigned int baud, quot;
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u32 tlr;
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switch (termios->c_cflag & CSIZE) {
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case CS5:
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@ -811,14 +824,28 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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up->mcr = serial_in(up, UART_MCR);
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serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
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/* FIFO ENABLE, DMA MODE */
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serial_out(up, UART_FCR, up->fcr);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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up->scr |= OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
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up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
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if (up->use_dma) {
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serial_out(up, UART_TI752_TLR, 0);
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up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
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tlr = 0;
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} else {
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up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
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/* Set receive FIFO threshold to 1 */
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up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
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up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
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/* Set TX FIFO threshold to "63" (actually 1) */
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up->fcr |= (0x3 << OMAP_UART_FCR_TX_FIFO_TRIG_SHIFT);
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tlr = (0xf << OMAP_UART_TLR_TX_FIFO_TRIG_DMA_SHIFT);
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}
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serial_out(up, UART_TI752_TLR, tlr);
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serial_out(up, UART_FCR, up->fcr);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_out(up, UART_OMAP_SCR, up->scr);
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serial_out(up, UART_EFR, up->efr);
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