[BNX2]: Enable DMA on 5709.
Add missing code to enable DMA on 5709 A1. The bit is a no-op on A0 and therefore can be set on all 5709 chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -3815,6 +3815,11 @@ bnx2_init_chip(struct bnx2 *bp)
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/* Initialize the receive filter. */
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/* Initialize the receive filter. */
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bnx2_set_rx_mode(bp->dev);
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bnx2_set_rx_mode(bp->dev);
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
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val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
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REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
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}
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rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
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rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
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0);
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0);
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@ -1373,6 +1373,7 @@ struct l2_fhdr {
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#define BNX2_MISC_NEW_CORE_CTL 0x000008c8
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#define BNX2_MISC_NEW_CORE_CTL 0x000008c8
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#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
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#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
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#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
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#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
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#define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
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#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
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#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
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#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
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#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
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