OMAP: DSS2: Clean up for dpll4_m4_ck handling
OMAP2 does not have dpll4_m4_ck source clock for dss functional clock, but later OMAPs do. Currently we check for cpu type in multiple places to find out if dpll4_m4_ck is available. This patch cleans up dss.c by using the fact that dss.dpll4_m4_ck pointer is NULL on OMAP2. This allows us to remove many of the cpu checks. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
Родитель
17c84ef1e1
Коммит
0acf659f14
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@ -239,30 +239,40 @@ void dss_dump_clocks(struct seq_file *s)
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{
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unsigned long dpll4_ck_rate;
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unsigned long dpll4_m4_ck_rate;
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const char *fclk_name, *fclk_real_name;
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unsigned long fclk_rate;
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
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seq_printf(s, "- DSS -\n");
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seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
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fclk_name = dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK);
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fclk_real_name = dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK);
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fclk_rate = dss_clk_get_rate(DSS_CLK_FCK);
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if (cpu_is_omap3630())
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seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
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dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
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dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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dss_clk_get_rate(DSS_CLK_FCK));
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else
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seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
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dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
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dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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dss_clk_get_rate(DSS_CLK_FCK));
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if (dss.dpll4_m4_ck) {
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dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
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seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
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if (cpu_is_omap3630())
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seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
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fclk_name, fclk_real_name,
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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fclk_rate);
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else
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seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
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fclk_name, fclk_real_name,
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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fclk_rate);
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} else {
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seq_printf(s, "%s (%s) = %lu\n",
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fclk_name, fclk_real_name,
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fclk_rate);
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}
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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}
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@ -382,31 +392,40 @@ enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
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/* calculate clock rates using dividers in cinfo */
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int dss_calc_clock_rates(struct dss_clock_info *cinfo)
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{
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unsigned long prate;
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if (dss.dpll4_m4_ck) {
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unsigned long prate;
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if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
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cinfo->fck_div == 0)
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return -EINVAL;
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if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
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cinfo->fck_div == 0)
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return -EINVAL;
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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cinfo->fck = prate / cinfo->fck_div;
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cinfo->fck = prate / cinfo->fck_div;
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} else {
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if (cinfo->fck_div != 0)
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return -EINVAL;
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cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
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}
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return 0;
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}
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int dss_set_clock_div(struct dss_clock_info *cinfo)
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{
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unsigned long prate;
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int r;
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if (dss.dpll4_m4_ck) {
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unsigned long prate;
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int r;
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if (cpu_is_omap34xx()) {
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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DSSDBG("dpll4_m4 = %ld\n", prate);
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r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
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if (r)
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return r;
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} else {
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if (cinfo->fck_div != 0)
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return -EINVAL;
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}
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DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
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@ -418,9 +437,11 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
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{
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cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
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if (cpu_is_omap34xx()) {
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if (dss.dpll4_m4_ck) {
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unsigned long prate;
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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if (cpu_is_omap3630())
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cinfo->fck_div = prate / (cinfo->fck);
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else
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@ -434,7 +455,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
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unsigned long dss_get_dpll4_rate(void)
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{
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if (cpu_is_omap34xx())
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if (dss.dpll4_m4_ck)
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return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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else
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return 0;
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@ -615,6 +636,7 @@ static int dss_init(void)
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int r;
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u32 rev;
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struct resource *dss_mem;
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struct clk *dpll4_m4_ck;
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dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
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if (!dss_mem) {
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@ -655,16 +677,19 @@ static int dss_init(void)
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REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
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REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
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#endif
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if (cpu_is_omap34xx()) {
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dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
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if (IS_ERR(dss.dpll4_m4_ck)) {
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dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
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if (IS_ERR(dpll4_m4_ck)) {
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DSSERR("Failed to get dpll4_m4_ck\n");
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r = PTR_ERR(dss.dpll4_m4_ck);
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r = PTR_ERR(dpll4_m4_ck);
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goto fail1;
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}
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} else { /* omap24xx */
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dpll4_m4_ck = NULL;
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}
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dss.dpll4_m4_ck = dpll4_m4_ck;
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dss.dsi_clk_source = DSS_CLK_SRC_FCK;
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dss.dispc_clk_source = DSS_CLK_SRC_FCK;
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dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
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@ -686,7 +711,7 @@ fail0:
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static void dss_exit(void)
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{
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if (cpu_is_omap34xx())
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if (dss.dpll4_m4_ck)
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clk_put(dss.dpll4_m4_ck);
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iounmap(dss.base);
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