of/pci: Fix the conversion of IO ranges into IO resources
The ranges property for a host bridge controller in DT describes the mapping between the PCI bus address and the CPU physical address. The resources framework however expects that the IO resources start at a pseudo "port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT. The conversion from PCI ranges to resources failed to take that into account, returning a CPU physical address instead of a port number. Also fix all the drivers that depend on the old behaviour by fetching the CPU physical address based on the port number where it is being needed. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Arnd Bergmann <arnd@arndb.de> CC: Thierry Reding <thierry.reding@gmail.com> CC: Simon Horman <horms@verge.net.au> CC: Catalin Marinas <catalin.marinas@arm.com>
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0b0b0893d4
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@ -660,6 +660,7 @@ static void __init pci_v3_preinit(void)
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{
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unsigned long flags;
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unsigned int temp;
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phys_addr_t io_address = pci_pio_to_address(io_mem.start);
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pcibios_min_mem = 0x00100000;
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@ -701,7 +702,7 @@ static void __init pci_v3_preinit(void)
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/*
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* Setup window 2 - PCI IO
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*/
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v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
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v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
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V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
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@ -742,6 +743,7 @@ static void __init pci_v3_preinit(void)
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static void __init pci_v3_postinit(void)
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{
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unsigned int pci_cmd;
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phys_addr_t io_address = pci_pio_to_address(io_mem.start);
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pci_cmd = PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
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@ -758,7 +760,7 @@ static void __init pci_v3_postinit(void)
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"interrupt: %d\n", ret);
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#endif
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register_isa_ports(non_mem.start, io_mem.start, 0);
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register_isa_ports(non_mem.start, io_address, 0);
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}
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/*
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@ -867,33 +869,32 @@ static int __init pci_v3_probe(struct platform_device *pdev)
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for_each_of_pci_range(&parser, &range) {
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if (!range.flags) {
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of_pci_range_to_resource(&range, np, &conf_mem);
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ret = of_pci_range_to_resource(&range, np, &conf_mem);
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conf_mem.name = "PCIv3 config";
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}
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if (range.flags & IORESOURCE_IO) {
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of_pci_range_to_resource(&range, np, &io_mem);
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ret = of_pci_range_to_resource(&range, np, &io_mem);
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io_mem.name = "PCIv3 I/O";
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}
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if ((range.flags & IORESOURCE_MEM) &&
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!(range.flags & IORESOURCE_PREFETCH)) {
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non_mem_pci = range.pci_addr;
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non_mem_pci_sz = range.size;
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of_pci_range_to_resource(&range, np, &non_mem);
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ret = of_pci_range_to_resource(&range, np, &non_mem);
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non_mem.name = "PCIv3 non-prefetched mem";
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}
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if ((range.flags & IORESOURCE_MEM) &&
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(range.flags & IORESOURCE_PREFETCH)) {
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pre_mem_pci = range.pci_addr;
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pre_mem_pci_sz = range.size;
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of_pci_range_to_resource(&range, np, &pre_mem);
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ret = of_pci_range_to_resource(&range, np, &pre_mem);
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pre_mem.name = "PCIv3 prefetched mem";
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}
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}
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if (!conf_mem.start || !io_mem.start ||
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!non_mem.start || !pre_mem.start) {
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dev_err(&pdev->dev, "missing ranges in device node\n");
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return -EINVAL;
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if (ret < 0) {
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dev_err(&pdev->dev, "missing ranges in device node\n");
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return ret;
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}
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}
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pci_v3.map_irq = of_irq_parse_and_map_pci;
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@ -295,14 +295,50 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
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}
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EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
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void of_pci_range_to_resource(struct of_pci_range *range,
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struct device_node *np, struct resource *res)
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/*
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* of_pci_range_to_resource - Create a resource from an of_pci_range
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* @range: the PCI range that describes the resource
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* @np: device node where the range belongs to
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* @res: pointer to a valid resource that will be updated to
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* reflect the values contained in the range.
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*
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* Returns EINVAL if the range cannot be converted to resource.
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*
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* Note that if the range is an IO range, the resource will be converted
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* using pci_address_to_pio() which can fail if it is called too early or
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* if the range cannot be matched to any host bridge IO space (our case here).
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* To guard against that we try to register the IO range first.
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* If that fails we know that pci_address_to_pio() will do too.
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*/
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int of_pci_range_to_resource(struct of_pci_range *range,
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struct device_node *np, struct resource *res)
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{
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int err;
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res->flags = range->flags;
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res->start = range->cpu_addr;
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res->end = range->cpu_addr + range->size - 1;
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res->parent = res->child = res->sibling = NULL;
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res->name = np->full_name;
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if (res->flags & IORESOURCE_IO) {
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unsigned long port;
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err = pci_register_io_range(range->cpu_addr, range->size);
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if (err)
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goto invalid_range;
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port = pci_address_to_pio(range->cpu_addr);
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if (port == (unsigned long)-1) {
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err = -EINVAL;
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goto invalid_range;
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}
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res->start = port;
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} else {
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res->start = range->cpu_addr;
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}
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res->end = res->start + range->size - 1;
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return 0;
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invalid_range:
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res->start = (resource_size_t)OF_BAD_ADDR;
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res->end = (resource_size_t)OF_BAD_ADDR;
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return err;
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}
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#endif /* CONFIG_PCI */
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@ -626,13 +626,14 @@ DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
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static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct tegra_pcie *pcie = sys_to_pcie(sys);
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phys_addr_t io_start = pci_pio_to_address(pcie->io.start);
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pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
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pci_add_resource_offset(&sys->resources, &pcie->prefetch,
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sys->mem_offset);
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pci_add_resource(&sys->resources, &pcie->busn);
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pci_ioremap_io(nr * SZ_64K, pcie->io.start);
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pci_ioremap_io(nr * SZ_64K, io_start);
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return 1;
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}
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@ -737,6 +738,7 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg)
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static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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{
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u32 fpci_bar, size, axi_address;
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phys_addr_t io_start = pci_pio_to_address(pcie->io.start);
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/* Bar 0: type 1 extended configuration space */
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fpci_bar = 0xfe100000;
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@ -749,7 +751,7 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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/* Bar 1: downstream IO bar */
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fpci_bar = 0xfdfc0000;
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size = resource_size(&pcie->io);
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axi_address = pcie->io.start;
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axi_address = io_start;
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afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
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@ -1520,7 +1522,9 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
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}
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for_each_of_pci_range(&parser, &range) {
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of_pci_range_to_resource(&range, np, &res);
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err = of_pci_range_to_resource(&range, np, &res);
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if (err < 0)
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return err;
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switch (res.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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@ -323,6 +323,7 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
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/* Setup PCIe address space mappings for each resource */
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resource_size_t size;
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resource_size_t res_start;
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u32 mask;
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rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
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@ -335,8 +336,13 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
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mask = (roundup_pow_of_two(size) / SZ_128) - 1;
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rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
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rcar_pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
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rcar_pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
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if (res->flags & IORESOURCE_IO)
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res_start = pci_pio_to_address(res->start);
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else
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res_start = res->start;
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rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
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rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win));
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/* First resource is for IO */
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mask = PAR_ENABLE;
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@ -363,9 +369,10 @@ static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
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rcar_pcie_setup_window(i, pcie);
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if (res->flags & IORESOURCE_IO)
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pci_ioremap_io(nr * SZ_64K, res->start);
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else
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if (res->flags & IORESOURCE_IO) {
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phys_addr_t io_start = pci_pio_to_address(res->start);
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pci_ioremap_io(nr * SZ_64K, io_start);
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} else
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pci_add_resource(&sys->resources, res);
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}
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pci_add_resource(&sys->resources, &pcie->busn);
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@ -935,8 +942,10 @@ static int rcar_pcie_probe(struct platform_device *pdev)
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}
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for_each_of_pci_range(&parser, &range) {
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of_pci_range_to_resource(&range, pdev->dev.of_node,
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err = of_pci_range_to_resource(&range, pdev->dev.of_node,
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&pcie->res[win++]);
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if (err < 0)
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return err;
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if (win > RCAR_PCI_MAX_RESOURCES)
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break;
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@ -134,9 +134,9 @@ extern const __be32 *of_get_pci_address(struct device_node *dev, int bar_no,
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u64 *size, unsigned int *flags);
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extern int of_pci_address_to_resource(struct device_node *dev, int bar,
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struct resource *r);
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extern void of_pci_range_to_resource(struct of_pci_range *range,
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struct device_node *np,
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struct resource *res);
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extern int of_pci_range_to_resource(struct of_pci_range *range,
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struct device_node *np,
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struct resource *res);
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#else /* CONFIG_OF_ADDRESS && CONFIG_PCI */
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static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
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struct resource *r)
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@ -149,9 +149,9 @@ static inline const __be32 *of_get_pci_address(struct device_node *dev,
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{
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return NULL;
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}
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static inline void of_pci_range_to_resource(struct of_pci_range *range,
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struct device_node *np,
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struct resource *res)
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static inline int of_pci_range_to_resource(struct of_pci_range *range,
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struct device_node *np,
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struct resource *res)
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{
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return -ENOSYS;
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}
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