x86, intel: Make MSR_IA32_MISC_ENABLE bit constants systematic
Replace somewhat arbitrary constants for bits in MSR_IA32_MISC_ENABLE with verbose but systematic ones. Add _BIT defines for all the rest of them, too. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
H. Peter Anvin
Родитель
c0a639ad0b
Коммит
0b131be8d4
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@ -368,36 +368,58 @@
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#define THERM_LOG_THRESHOLD1 (1 << 9)
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/* MISC_ENABLE bits: architectural */
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#define MSR_BIT_FAST_STRING 0
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#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_BIT_FAST_STRING)
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#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
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#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
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#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
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#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
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#define MSR_BIT_LIMIT_CPUID 22
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_BIT_LIMIT_CPUID);
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
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#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
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#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
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#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
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#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
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#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
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#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
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#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
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#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
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#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
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#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT);
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
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/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
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#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
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#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
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#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
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#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
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#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
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#define MSR_BIT_PRF_DIS 9
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#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_BIT_PRF_DIS)
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#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
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#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
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#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
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#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
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#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
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#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
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#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
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#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
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#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
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#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
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#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
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#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
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#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
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#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
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#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
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#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
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#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
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#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
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#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
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#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
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#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
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#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
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#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
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#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
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#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
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#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
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#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
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#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
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#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
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#define MSR_IA32_TSC_DEADLINE 0x000006E0
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@ -31,7 +31,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
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/* Unmask CPUID levels if masked: */
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if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
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if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_LIMIT_CPUID) > 0) {
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if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
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MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
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c->cpuid_level = cpuid_eax(0);
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get_cpu_cap(c);
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}
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@ -126,7 +127,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
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* (model 2) with the same problem.
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*/
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if (c->x86 == 15)
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if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_FAST_STRING) > 0)
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if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
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MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
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pr_info("kmemcheck: Disabling fast string operations\n");
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#endif
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@ -216,7 +218,9 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
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* Hardware prefetcher may cause stale data to be loaded into the cache.
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*/
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if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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if (msr_set_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_PRF_DIS) > 0) {
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if (msr_set_bit(MSR_IA32_MISC_ENABLE,
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MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
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> 0) {
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pr_info("CPU: C0 stepping P4 Xeon detected.\n");
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pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
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}
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