Merge branch 'perf/urgent' into perf/core, to resolve conflict
Conflicts: arch/x86/events/intel/pt.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
Коммит
0b20e59cef
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@ -115,7 +115,7 @@ static __initconst const u64 amd_hw_cache_event_ids
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/*
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* AMD Performance Monitor K7 and later.
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*/
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static const u64 amd_perfmon_event_map[] =
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static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
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@ -64,7 +64,7 @@ static enum {
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#define LBR_PLM (LBR_KERNEL | LBR_USER)
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#define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
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#define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
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#define LBR_NOT_SUPP -1 /* LBR filter not supported */
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#define LBR_IGN 0 /* ignored */
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@ -621,8 +621,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
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* The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
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* in suppress mode. So LBR_SELECT should be set to
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* (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
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* But the 10th bit LBR_CALL_STACK does not operate
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* in suppress mode.
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*/
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reg->config = mask ^ x86_pmu.lbr_sel_mask;
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reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
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if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
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(br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
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@ -136,9 +136,21 @@ static int __init pt_pmu_hw_init(void)
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struct dev_ext_attribute *de_attrs;
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struct attribute **attrs;
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size_t size;
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u64 reg;
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int ret;
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long i;
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if (boot_cpu_has(X86_FEATURE_VMX)) {
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/*
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* Intel SDM, 36.5 "Tracing post-VMXON" says that
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* "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
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* post-VMXON.
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*/
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rdmsrl(MSR_IA32_VMX_MISC, reg);
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if (reg & BIT(14))
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pt_pmu.vmx = true;
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}
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attrs = NULL;
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for (i = 0; i < PT_CPUID_LEAVES; i++) {
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@ -269,20 +281,23 @@ static void pt_config(struct perf_event *event)
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reg |= (event->attr.config & PT_CONFIG_MASK);
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event->hw.config = reg;
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wrmsrl(MSR_IA32_RTIT_CTL, reg);
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}
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static void pt_config_start(bool start)
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static void pt_config_stop(struct perf_event *event)
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{
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u64 ctl;
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u64 ctl = READ_ONCE(event->hw.config);
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rdmsrl(MSR_IA32_RTIT_CTL, ctl);
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if (start)
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ctl |= RTIT_CTL_TRACEEN;
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else
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ctl &= ~RTIT_CTL_TRACEEN;
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/* may be already stopped by a PMI */
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if (!(ctl & RTIT_CTL_TRACEEN))
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return;
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ctl &= ~RTIT_CTL_TRACEEN;
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wrmsrl(MSR_IA32_RTIT_CTL, ctl);
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WRITE_ONCE(event->hw.config, ctl);
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/*
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* A wrmsr that disables trace generation serializes other PT
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* registers and causes all data packets to be written to memory,
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@ -291,8 +306,7 @@ static void pt_config_start(bool start)
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* The below WMB, separating data store and aux_head store matches
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* the consumer's RMB that separates aux_head load and data load.
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*/
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if (!start)
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wmb();
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wmb();
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}
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static void pt_config_buffer(void *buf, unsigned int topa_idx,
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@ -922,11 +936,17 @@ void intel_pt_interrupt(void)
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if (!ACCESS_ONCE(pt->handle_nmi))
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return;
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pt_config_start(false);
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/*
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* If VMX is on and PT does not support it, don't touch anything.
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*/
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if (READ_ONCE(pt->vmx_on))
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return;
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if (!event)
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return;
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pt_config_stop(event);
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buf = perf_get_aux(&pt->handle);
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if (!buf)
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return;
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@ -963,6 +983,35 @@ void intel_pt_interrupt(void)
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}
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}
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void intel_pt_handle_vmx(int on)
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{
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struct pt *pt = this_cpu_ptr(&pt_ctx);
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struct perf_event *event;
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unsigned long flags;
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/* PT plays nice with VMX, do nothing */
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if (pt_pmu.vmx)
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return;
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/*
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* VMXON will clear RTIT_CTL.TraceEn; we need to make
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* sure to not try to set it while VMX is on. Disable
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* interrupts to avoid racing with pmu callbacks;
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* concurrent PMI should be handled fine.
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*/
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local_irq_save(flags);
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WRITE_ONCE(pt->vmx_on, on);
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if (on) {
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/* prevent pt_config_stop() from writing RTIT_CTL */
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event = pt->handle.event;
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if (event)
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event->hw.config = 0;
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}
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
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/*
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* PMU callbacks
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*/
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@ -973,6 +1022,9 @@ static void pt_event_start(struct perf_event *event, int mode)
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struct pt *pt = this_cpu_ptr(&pt_ctx);
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struct pt_buffer *buf;
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if (READ_ONCE(pt->vmx_on))
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return;
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buf = perf_aux_output_begin(&pt->handle, event);
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if (!buf)
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goto fail_stop;
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@ -1007,7 +1059,8 @@ static void pt_event_stop(struct perf_event *event, int mode)
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* see comment in intel_pt_interrupt().
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*/
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ACCESS_ONCE(pt->handle_nmi) = 0;
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pt_config_start(false);
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pt_config_stop(event);
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if (event->hw.state == PERF_HES_STOPPED)
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return;
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@ -65,6 +65,7 @@ enum pt_capabilities {
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struct pt_pmu {
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struct pmu pmu;
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u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
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bool vmx;
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};
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/**
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@ -107,10 +108,12 @@ struct pt_buffer {
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* struct pt - per-cpu pt context
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* @handle: perf output handle
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* @handle_nmi: do handle PT PMI on this cpu, there's an active event
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* @vmx_on: 1 if VMX is ON on this cpu
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*/
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struct pt {
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struct perf_output_handle handle;
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int handle_nmi;
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int vmx_on;
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};
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#endif /* __INTEL_PT_H__ */
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@ -285,6 +285,10 @@ static inline void perf_events_lapic_init(void) { }
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static inline void perf_check_microcode(void) { }
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#endif
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#ifdef CONFIG_CPU_SUP_INTEL
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extern void intel_pt_handle_vmx(int on);
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#endif
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
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extern void amd_pmu_enable_virt(void);
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extern void amd_pmu_disable_virt(void);
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@ -3103,6 +3103,8 @@ static __init int vmx_disabled_by_bios(void)
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static void kvm_cpu_vmxon(u64 addr)
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{
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intel_pt_handle_vmx(1);
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asm volatile (ASM_VMX_VMXON_RAX
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: : "a"(&addr), "m"(addr)
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: "memory", "cc");
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@ -3172,6 +3174,8 @@ static void vmclear_local_loaded_vmcss(void)
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static void kvm_cpu_vmxoff(void)
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{
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asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
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intel_pt_handle_vmx(0);
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}
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static void hardware_disable(void)
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@ -1106,6 +1106,7 @@ static void put_ctx(struct perf_event_context *ctx)
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* function.
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*
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* Lock order:
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* cred_guard_mutex
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* task_struct::perf_event_mutex
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* perf_event_context::mutex
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* perf_event::child_mutex;
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@ -3449,7 +3450,6 @@ static struct task_struct *
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find_lively_task_by_vpid(pid_t vpid)
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{
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struct task_struct *task;
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int err;
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rcu_read_lock();
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if (!vpid)
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@ -3463,16 +3463,7 @@ find_lively_task_by_vpid(pid_t vpid)
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if (!task)
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return ERR_PTR(-ESRCH);
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/* Reuse ptrace permission checks for now. */
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err = -EACCES;
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if (!ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
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goto errout;
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return task;
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errout:
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put_task_struct(task);
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return ERR_PTR(err);
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}
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/*
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@ -8592,6 +8583,24 @@ SYSCALL_DEFINE5(perf_event_open,
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get_online_cpus();
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if (task) {
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err = mutex_lock_interruptible(&task->signal->cred_guard_mutex);
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if (err)
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goto err_cpus;
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/*
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* Reuse ptrace permission checks for now.
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*
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* We must hold cred_guard_mutex across this and any potential
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* perf_install_in_context() call for this new event to
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* serialize against exec() altering our credentials (and the
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* perf_event_exit_task() that could imply).
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*/
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err = -EACCES;
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if (!ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
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goto err_cred;
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}
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if (flags & PERF_FLAG_PID_CGROUP)
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cgroup_fd = pid;
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@ -8599,7 +8608,7 @@ SYSCALL_DEFINE5(perf_event_open,
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NULL, NULL, cgroup_fd);
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if (IS_ERR(event)) {
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err = PTR_ERR(event);
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goto err_cpus;
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goto err_cred;
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}
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if (is_sampling_event(event)) {
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@ -8658,11 +8667,6 @@ SYSCALL_DEFINE5(perf_event_open,
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goto err_context;
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}
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if (task) {
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put_task_struct(task);
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task = NULL;
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}
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/*
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* Look up the group leader (we will attach this event to it):
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*/
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@ -8760,6 +8764,11 @@ SYSCALL_DEFINE5(perf_event_open,
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WARN_ON_ONCE(ctx->parent_ctx);
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/*
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* This is the point on no return; we cannot fail hereafter. This is
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* where we start modifying current state.
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*/
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if (move_group) {
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/*
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* See perf_event_ctx_lock() for comments on the details
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@ -8831,6 +8840,11 @@ SYSCALL_DEFINE5(perf_event_open,
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mutex_unlock(&gctx->mutex);
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mutex_unlock(&ctx->mutex);
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if (task) {
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mutex_unlock(&task->signal->cred_guard_mutex);
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put_task_struct(task);
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}
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put_online_cpus();
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mutex_lock(¤t->perf_event_mutex);
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@ -8863,6 +8877,9 @@ err_alloc:
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*/
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if (!event_file)
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free_event(event);
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err_cred:
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if (task)
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mutex_unlock(&task->signal->cred_guard_mutex);
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err_cpus:
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put_online_cpus();
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err_task:
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@ -9147,6 +9164,9 @@ static void perf_event_exit_task_context(struct task_struct *child, int ctxn)
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/*
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* When a child task exits, feed back event values to parent events.
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*
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* Can be called with cred_guard_mutex held when called from
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* install_exec_creds().
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*/
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void perf_event_exit_task(struct task_struct *child)
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{
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