[POWERPC] 8xx: Convert mpc866ads to the new device binding.
Verified on mpc866ads. This version has muram and brg nodes added to dts to get the things work. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
This commit is contained in:
Scott Wood
Kumar Gala
Родитель
77d4309e19
Коммит
0b5cf10691
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@ -12,7 +12,7 @@
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/ {
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model = "MPC866ADS";
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compatible = "mpc8xx";
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compatible = "fsl,mpc866ads";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -23,15 +23,15 @@
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PowerPC,866@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-line-size = <10>; // 16 bytes
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i-cache-line-size = <10>; // 16 bytes
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d-cache-size = <2000>; // L1, 8K
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i-cache-size = <4000>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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interrupts = <f 2>; // decrementer interrupt
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interrupt-parent = <&Mpc8xx_pic>;
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interrupt-parent = <&PIC>;
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};
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};
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@ -40,107 +40,139 @@
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reg = <00000000 800000>;
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};
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soc866@ff000000 {
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localbus@ff000100 {
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compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <ff000100 40>;
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ranges = <
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1 0 ff080000 00008000
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5 0 ff0a0000 00008000
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>;
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board-control@1,0 {
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reg = <1 0 20 5 300 4>;
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compatible = "fsl,mpc866ads-bcsr";
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};
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};
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soc@ff000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 ff000000 00100000>;
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reg = <ff000000 00000200>;
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bus-frequency = <0>;
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mdio@e80 {
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device_type = "mdio";
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compatible = "fs_enet";
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reg = <e80 8>;
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mdio@e00 {
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compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
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reg = <e00 188>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@f {
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PHY: ethernet-phy@f {
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reg = <f>;
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device_type = "ethernet-phy";
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};
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};
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fec@e00 {
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ethernet@e00 {
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device_type = "network";
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compatible = "fs_enet";
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model = "FEC";
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device-id = <1>;
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compatible = "fsl,mpc866-fec-enet",
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"fsl,pq1-fec-enet";
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reg = <e00 188>;
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mac-address = [ 00 00 0C 00 01 FD ];
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <3 1>;
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interrupt-parent = <&Mpc8xx_pic>;
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phy-handle = <&Phy>;
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interrupt-parent = <&PIC>;
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phy-handle = <&PHY>;
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linux,network-index = <0>;
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};
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mpc8xx_pic: pic@ff000000 {
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PIC: pic@0 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0 24>;
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device_type = "mpc8xx-pic";
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compatible = "CPM";
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compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
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};
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cpm@ff000000 {
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cpm@9c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "cpm";
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model = "CPM";
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ranges = <0 0 4000>;
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reg = <860 f0>;
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command-proc = <9c0>;
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compatible = "fsl,mpc866-cpm", "fsl,cpm1";
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ranges;
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reg = <9c0 40>;
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brg-frequency = <0>;
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interrupts = <0 2>; // cpm error interrupt
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interrupt-parent = <&Cpm_pic>;
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interrupt-parent = <&CPM_PIC>;
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cpm_pic: pic@930 {
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muram@2000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 2000 2000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0 1c00>;
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};
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};
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brg@9f0 {
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compatible = "fsl,mpc866-brg",
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"fsl,cpm1-brg",
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"fsl,cpm-brg";
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reg = <9f0 10>;
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clock-frequency = <0>;
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};
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CPM_PIC: pic@930 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <5 2 0 2>;
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interrupt-parent = <&Mpc8xx_pic>;
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interrupt-parent = <&PIC>;
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reg = <930 20>;
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device_type = "cpm-pic";
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compatible = "CPM";
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compatible = "fsl,mpc866-cpm-pic",
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"fsl,cpm1-pic";
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};
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smc@a80 {
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serial@a80 {
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device_type = "serial";
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compatible = "cpm_uart";
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model = "SMC";
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device-id = <1>;
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compatible = "fsl,mpc866-smc-uart",
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"fsl,cpm1-smc-uart";
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reg = <a80 10 3e80 40>;
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clock-setup = <00ffffff 0>;
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rx-clock = <1>;
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tx-clock = <1>;
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current-speed = <0>;
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interrupts = <4 3>;
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interrupt-parent = <&Cpm_pic>;
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interrupts = <4>;
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interrupt-parent = <&CPM_PIC>;
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fsl,cpm-brg = <1>;
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fsl,cpm-command = <0090>;
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};
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smc@a90 {
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serial@a90 {
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device_type = "serial";
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compatible = "cpm_uart";
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model = "SMC";
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device-id = <2>;
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reg = <a90 20 3f80 40>;
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clock-setup = <ff00ffff 90000>;
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rx-clock = <2>;
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tx-clock = <2>;
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current-speed = <0>;
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interrupts = <3 3>;
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interrupt-parent = <&Cpm_pic>;
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compatible = "fsl,mpc866-smc-uart",
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"fsl,cpm1-smc-uart";
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reg = <a90 10 3f80 40>;
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interrupts = <3>;
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interrupt-parent = <&CPM_PIC>;
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fsl,cpm-brg = <2>;
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fsl,cpm-command = <00d0>;
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};
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scc@a00 {
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ethernet@a00 {
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device_type = "network";
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compatible = "fs_enet";
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model = "SCC";
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device-id = <1>;
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reg = <a00 18 3c00 80>;
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mac-address = [ 00 00 0C 00 03 FD ];
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interrupts = <1e 3>;
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interrupt-parent = <&Cpm_pic>;
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compatible = "fsl,mpc866-scc-enet",
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"fsl,cpm1-scc-enet";
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reg = <a00 18 3c00 100>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1e>;
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interrupt-parent = <&CPM_PIC>;
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fsl,cpm-command = <0000>;
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linux,network-index = <1>;
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};
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};
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};
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chosen {
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linux,stdout-path = "/soc/cpm/serial@a80";
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};
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};
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@ -18,6 +18,7 @@ config MPC8XXFADS
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config MPC86XADS
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bool "MPC86XADS"
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select CPM1
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select PPC_CPM_NEW_BINDING
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help
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MPC86x Application Development System by Freescale Semiconductor.
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The MPC86xADS is meant to serve as a platform for s/w and h/w
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@ -15,27 +15,6 @@
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#ifndef __ASM_MPC86XADS_H__
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#define __ASM_MPC86XADS_H__
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#include <sysdev/fsl_soc.h>
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/* U-Boot maps BCSR to 0xff080000 */
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#define BCSR_ADDR ((uint)0xff080000)
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#define BCSR_SIZE ((uint)32)
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#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
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#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
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#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
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#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
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#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
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#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
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#define MPC8xx_CPM_OFFSET (0x9c0)
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#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
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#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
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#define PCMCIA_MEM_ADDR ((uint)0xff020000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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/* Bits of interest in the BCSRs.
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*/
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#define BCSR1_ETHEN ((uint)0x20000000)
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@ -64,28 +43,5 @@
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#define BCSR5_MII1_EN 0x02
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#define BCSR5_MII1_RST 0x01
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/* Interrupt level assignments */
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#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
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#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
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#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
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/* We don't use the 8259 */
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#define NR_8259_INTS 0
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/* CPM Ethernet through SCC1 */
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#define PA_ENET_RXD ((ushort)0x0001)
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#define PA_ENET_TXD ((ushort)0x0002)
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#define PA_ENET_TCLK ((ushort)0x0100)
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#define PA_ENET_RCLK ((ushort)0x0200)
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#define PB_ENET_TENA ((uint)0x00001000)
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#define PC_ENET_CLSN ((ushort)0x0010)
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#define PC_ENET_RENA ((ushort)0x0020)
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/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
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* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x000000ff)
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#define SICR_ENET_CLKRT ((uint)0x0000002c)
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#endif /* __ASM_MPC86XADS_H__ */
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#endif /* __KERNEL__ */
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@ -6,265 +6,135 @@
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*
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* Copyright 2005 MontaVista Software Inc.
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*
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* Heavily modified by Scott Wood <scottwood@freescale.com>
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/root_dev.h>
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#include <linux/of_platform.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/fs_uart_pd.h>
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#include <linux/mii.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/mpc8xx.h>
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#include <asm/8xx_immap.h>
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#include <asm/commproc.h>
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#include <asm/fs_pd.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <sysdev/commproc.h>
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static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
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static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
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static void init_scc1_ioports(struct fs_platform_info* ptr);
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#include "mpc86xads.h"
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void __init mpc86xads_board_setup(void)
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struct cpm_pin {
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int port, pin, flags;
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};
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static struct cpm_pin mpc866ads_pins[] = {
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/* SMC1 */
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{CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
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{CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
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/* SMC2 */
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{CPM_PORTB, 21, CPM_PIN_INPUT}, /* RX */
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{CPM_PORTB, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
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/* SCC1 */
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{CPM_PORTA, 6, CPM_PIN_INPUT}, /* CLK1 */
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{CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
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{CPM_PORTA, 14, CPM_PIN_INPUT}, /* TX */
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{CPM_PORTA, 15, CPM_PIN_INPUT}, /* RX */
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{CPM_PORTB, 19, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
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{CPM_PORTC, 10, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
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{CPM_PORTC, 11, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
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/* MII */
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{CPM_PORTD, 3, CPM_PIN_OUTPUT},
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{CPM_PORTD, 4, CPM_PIN_OUTPUT},
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{CPM_PORTD, 5, CPM_PIN_OUTPUT},
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{CPM_PORTD, 6, CPM_PIN_OUTPUT},
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{CPM_PORTD, 7, CPM_PIN_OUTPUT},
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{CPM_PORTD, 8, CPM_PIN_OUTPUT},
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{CPM_PORTD, 9, CPM_PIN_OUTPUT},
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{CPM_PORTD, 10, CPM_PIN_OUTPUT},
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{CPM_PORTD, 11, CPM_PIN_OUTPUT},
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{CPM_PORTD, 12, CPM_PIN_OUTPUT},
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{CPM_PORTD, 13, CPM_PIN_OUTPUT},
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{CPM_PORTD, 14, CPM_PIN_OUTPUT},
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{CPM_PORTD, 15, CPM_PIN_OUTPUT},
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};
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static void __init init_ioports(void)
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{
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cpm8xx_t *cp;
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unsigned int *bcsr_io;
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u8 tmpval8;
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int i;
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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cp = (cpm8xx_t *)immr_map(im_cpm);
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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#ifdef CONFIG_SERIAL_CPM_SMC1
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clrbits32(bcsr_io, BCSR1_RS232EN_1);
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clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
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tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
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out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
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clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_1);
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out_be16(&cp->cp_smc[0].smc_smcmr, 0);
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out_8(&cp->cp_smc[0].smc_smce, 0);
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#endif
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#ifdef CONFIG_SERIAL_CPM_SMC2
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clrbits32(bcsr_io,BCSR1_RS232EN_2);
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clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
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setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
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tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
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out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
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clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
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init_smc2_uart_ioports(0);
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_2);
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out_be16(&cp->cp_smc[1].smc_smcmr, 0);
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out_8(&cp->cp_smc[1].smc_smce, 0);
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#endif
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immr_unmap(cp);
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iounmap(bcsr_io);
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for (i = 0; i < ARRAY_SIZE(mpc866ads_pins); i++) {
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struct cpm_pin *pin = &mpc866ads_pins[i];
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cpm1_set_pin(pin->port, pin->pin, pin->flags);
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}
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cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
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cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
|
||||
cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK1, CPM_CLK_TX);
|
||||
cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
|
||||
|
||||
static void init_fec1_ioports(struct fs_platform_info* ptr)
|
||||
{
|
||||
iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
|
||||
|
||||
/* configure FEC1 pins */
|
||||
|
||||
setbits16(&io_port->iop_pdpar, 0x1fff);
|
||||
setbits16(&io_port->iop_pddir, 0x1fff);
|
||||
|
||||
immr_unmap(io_port);
|
||||
}
|
||||
|
||||
void init_fec_ioports(struct fs_platform_info *fpi)
|
||||
{
|
||||
int fec_no = fs_get_fec_index(fpi->fs_no);
|
||||
|
||||
switch (fec_no) {
|
||||
case 0:
|
||||
init_fec1_ioports(fpi);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void init_scc1_ioports(struct fs_platform_info* fpi)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
iop8xx_t *io_port;
|
||||
cpm8xx_t *cp;
|
||||
|
||||
bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
|
||||
io_port = (iop8xx_t *)immr_map(im_ioport);
|
||||
cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Configure port A pins for Txd and Rxd.
|
||||
*/
|
||||
setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
|
||||
clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
|
||||
clrbits16(&io_port->iop_paodr, PA_ENET_TXD);
|
||||
|
||||
/* Configure port C pins to enable CLSN and RENA.
|
||||
*/
|
||||
clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
|
||||
/* Configure port A for TCLK and RCLK.
|
||||
*/
|
||||
setbits16(&io_port->iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
|
||||
clrbits16(&io_port->iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
|
||||
clrbits32(&cp->cp_pbpar, PB_ENET_TENA);
|
||||
clrbits32(&cp->cp_pbdir, PB_ENET_TENA);
|
||||
|
||||
/* Configure Serial Interface clock routing.
|
||||
* First, clear all SCC bits to zero, then set the ones we want.
|
||||
*/
|
||||
clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
|
||||
setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
|
||||
|
||||
/* In the original SCC enet driver the following code is placed at
|
||||
the end of the initialization */
|
||||
setbits32(&cp->cp_pbpar, PB_ENET_TENA);
|
||||
setbits32(&cp->cp_pbdir, PB_ENET_TENA);
|
||||
|
||||
clrbits32(bcsr_io+1, BCSR1_ETHEN);
|
||||
iounmap(bcsr_io);
|
||||
immr_unmap(cp);
|
||||
immr_unmap(io_port);
|
||||
}
|
||||
|
||||
void init_scc_ioports(struct fs_platform_info *fpi)
|
||||
{
|
||||
int scc_no = fs_get_scc_index(fpi->fs_no);
|
||||
|
||||
switch (scc_no) {
|
||||
case 0:
|
||||
init_scc1_ioports(fpi);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
setbits32(&cp->cp_pbpar, 0x000000c0);
|
||||
clrbits32(&cp->cp_pbdir, 0x000000c0);
|
||||
clrbits16(&cp->cp_pbodr, 0x00c0);
|
||||
immr_unmap(cp);
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
setbits32(&cp->cp_pbpar, 0x00000c00);
|
||||
clrbits32(&cp->cp_pbdir, 0x00000c00);
|
||||
clrbits16(&cp->cp_pbodr, 0x0c00);
|
||||
immr_unmap(cp);
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
void init_smc_ioports(struct fs_uart_platform_info *data)
|
||||
{
|
||||
int smc_no = fs_uart_id_fsid2smc(data->fs_no);
|
||||
|
||||
switch (smc_no) {
|
||||
case 0:
|
||||
init_smc1_uart_ioports(data);
|
||||
data->brg = data->clk_rx;
|
||||
break;
|
||||
case 1:
|
||||
init_smc2_uart_ioports(data);
|
||||
data->brg = data->clk_rx;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
int platform_device_skip(const char *model, int id)
|
||||
{
|
||||
return 0;
|
||||
/* Set FEC1 and FEC2 to MII mode */
|
||||
clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
|
||||
}
|
||||
|
||||
static void __init mpc86xads_setup_arch(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 __iomem *bcsr_io;
|
||||
|
||||
cpm_reset();
|
||||
init_ioports();
|
||||
|
||||
mpc86xads_board_setup();
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,mpc866ads-bcsr");
|
||||
if (!np) {
|
||||
printk(KERN_CRIT "Could not find fsl,mpc866ads-bcsr node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ROOT_DEV = Root_NFS;
|
||||
bcsr_io = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
static int __init mpc86xads_probe(void)
|
||||
{
|
||||
char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
|
||||
"model", NULL);
|
||||
if (model == NULL)
|
||||
return 0;
|
||||
if (strcmp(model, "MPC866ADS"))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
return of_flat_dt_is_compatible(root, "fsl,mpc866ads");
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata of_bus_ids[] = {
|
||||
{ .name = "soc", },
|
||||
{ .name = "cpm", },
|
||||
{ .name = "localbus", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init declare_of_platform_devices(void)
|
||||
{
|
||||
if (machine_is(mpc86x_ads))
|
||||
of_platform_bus_probe(NULL, of_bus_ids, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(declare_of_platform_devices);
|
||||
|
||||
define_machine(mpc86x_ads) {
|
||||
.name = "MPC86x ADS",
|
||||
.probe = mpc86xads_probe,
|
||||
|
|
@ -275,4 +145,5 @@ define_machine(mpc86x_ads) {
|
|||
.calibrate_decr = mpc8xx_calibrate_decr,
|
||||
.set_rtc_time = mpc8xx_set_rtc_time,
|
||||
.get_rtc_time = mpc8xx_get_rtc_time,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
|
|
|
|||
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