gpio: brcmstb: consolidate interrupt domains
The GPIOLIB IRQ chip helpers were very appealing, but badly broke
the 1:1 mapping between a GPIO controller's device_node and its
interrupt domain.
When another device-tree node references a GPIO device as its
interrupt parent, the irq_create_of_mapping() function looks for
the irq domain of the GPIO device and since all bank irq domains
reference the same GPIO device node it always resolves to the irq
domain of the first bank regardless of which bank the number of
the GPIO should resolve. This domain can only map hwirq numbers
0-31 so interrupts on GPIO above that can't be mapped by the
device-tree.
This commit effectively reverts the patch from Gregory Fong [1]
that was accepted upstream and replaces it with a consolidated
irq domain implementation with one larger interrupt domain per
GPIO controller instance spanning multiple GPIO banks based on
an earlier patch [2] also submitted by Gregory Fong.
[1] https://patchwork.kernel.org/patch/6921561/
[2] https://patchwork.kernel.org/patch/6347811/
Fixes: 19a7b6940b ("gpio: brcmstb: Add interrupt and wakeup source support")
Signed-off-by: Doug Berger <opendmb@gmail.com>
Reviewed-by: Gregory Fong <gregory.0xf0@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Doug Berger
Linus Walleij
Родитель
633007a36e
Коммит
0ba31dc201
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@ -139,7 +139,7 @@ config GPIO_BRCMSTB
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default y if (ARCH_BRCMSTB || BMIPS_GENERIC)
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depends on OF_GPIO && (ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST)
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select GPIO_GENERIC
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select GPIOLIB_IRQCHIP
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select IRQ_DOMAIN
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help
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Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
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@ -38,20 +38,22 @@ struct brcmstb_gpio_bank {
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struct gpio_chip gc;
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struct brcmstb_gpio_priv *parent_priv;
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u32 width;
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struct irq_chip irq_chip;
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};
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struct brcmstb_gpio_priv {
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struct list_head bank_list;
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void __iomem *reg_base;
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struct platform_device *pdev;
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struct irq_domain *irq_domain;
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struct irq_chip irq_chip;
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int parent_irq;
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int gpio_base;
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int num_gpios;
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int parent_wake_irq;
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struct notifier_block reboot_notifier;
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};
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#define MAX_GPIO_PER_BANK 32
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#define MAX_GPIO_PER_BANK 32
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#define GPIO_BANK(gpio) ((gpio) >> 5)
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/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
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#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
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@ -78,24 +80,42 @@ brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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return status;
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}
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static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
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struct brcmstb_gpio_bank *bank)
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{
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return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
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}
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static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
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unsigned int offset, bool enable)
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unsigned int hwirq, bool enable)
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{
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struct gpio_chip *gc = &bank->gc;
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
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u32 imask;
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
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if (enable)
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imask |= BIT(offset);
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imask |= mask;
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else
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imask &= ~BIT(offset);
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imask &= ~mask;
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gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
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/* gc_offset is relative to this gpio_chip; want real offset */
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int hwirq = offset + (gc->base - priv->gpio_base);
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if (hwirq >= priv->num_gpios)
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return -ENXIO;
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return irq_create_mapping(priv->irq_domain, hwirq);
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}
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/* -------------------- IRQ chip functions -------------------- */
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static void brcmstb_gpio_irq_mask(struct irq_data *d)
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@ -119,7 +139,7 @@ static void brcmstb_gpio_irq_ack(struct irq_data *d)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(d->hwirq);
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
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gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
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}
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@ -129,7 +149,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(d->hwirq);
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
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u32 edge_insensitive, iedge_insensitive;
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u32 edge_config, iedge_config;
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u32 level, ilevel;
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@ -226,18 +246,20 @@ static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
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static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
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{
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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struct irq_domain *irq_domain = bank->gc.irqdomain;
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struct irq_domain *domain = priv->irq_domain;
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int hwbase = bank->gc.base - priv->gpio_base;
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unsigned long status;
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while ((status = brcmstb_gpio_get_active_irqs(bank))) {
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int bit;
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unsigned int irq, offset;
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for_each_set_bit(bit, &status, 32) {
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if (bit >= bank->width)
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for_each_set_bit(offset, &status, 32) {
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if (offset >= bank->width)
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dev_warn(&priv->pdev->dev,
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"IRQ for invalid GPIO (bank=%d, offset=%d)\n",
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bank->id, bit);
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generic_handle_irq(irq_find_mapping(irq_domain, bit));
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bank->id, offset);
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irq = irq_linear_revmap(domain, hwbase + offset);
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generic_handle_irq(irq);
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}
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}
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}
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@ -245,8 +267,7 @@ static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
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/* Each UPG GIO block has one IRQ for all banks */
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static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
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struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct brcmstb_gpio_bank *bank;
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@ -272,6 +293,63 @@ static int brcmstb_gpio_reboot(struct notifier_block *nb,
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return NOTIFY_DONE;
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}
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static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
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struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
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{
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struct brcmstb_gpio_bank *bank;
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int i = 0;
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/* banks are in descending order */
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list_for_each_entry_reverse(bank, &priv->bank_list, node) {
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i += bank->gc.ngpio;
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if (hwirq < i)
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return bank;
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}
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return NULL;
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}
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/*
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* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key brcmstb_gpio_irq_lock_class;
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static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct brcmstb_gpio_priv *priv = d->host_data;
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struct brcmstb_gpio_bank *bank =
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brcmstb_gpio_hwirq_to_bank(priv, hwirq);
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struct platform_device *pdev = priv->pdev;
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int ret;
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if (!bank)
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return -EINVAL;
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dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
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irq, (int)hwirq, bank->id);
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ret = irq_set_chip_data(irq, &bank->gc);
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if (ret < 0)
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return ret;
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irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class);
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irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
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irq_set_noprobe(irq);
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return 0;
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}
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static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
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.map = brcmstb_gpio_irq_map,
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.unmap = brcmstb_gpio_irq_unmap,
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.xlate = irq_domain_xlate_twocell,
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};
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/* Make sure that the number of banks matches up between properties */
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static int brcmstb_gpio_sanity_check_banks(struct device *dev,
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struct device_node *np, struct resource *res)
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@ -293,13 +371,25 @@ static int brcmstb_gpio_remove(struct platform_device *pdev)
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{
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struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
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struct brcmstb_gpio_bank *bank;
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int ret = 0;
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int offset, ret = 0, virq;
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if (!priv) {
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dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
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return -EFAULT;
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}
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if (priv->parent_irq > 0)
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irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
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/* Remove all IRQ mappings and delete the domain */
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if (priv->irq_domain) {
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for (offset = 0; offset < priv->num_gpios; offset++) {
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virq = irq_find_mapping(priv->irq_domain, offset);
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irq_dispose_mapping(virq);
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}
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irq_domain_remove(priv->irq_domain);
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}
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/*
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* You can lose return values below, but we report all errors, and it's
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* more important to actually perform all of the steps.
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@ -347,26 +437,24 @@ static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
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return offset;
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}
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/* Before calling, must have bank->parent_irq set and gpiochip registered */
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/* priv->parent_irq and priv->num_gpios must be set before calling */
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static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
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struct brcmstb_gpio_bank *bank)
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struct brcmstb_gpio_priv *priv)
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{
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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int err;
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bank->irq_chip.name = dev_name(dev);
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bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
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bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
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bank->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
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bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
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priv->irq_domain =
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irq_domain_add_linear(np, priv->num_gpios,
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&brcmstb_gpio_irq_domain_ops,
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priv);
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if (!priv->irq_domain) {
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dev_err(dev, "Couldn't allocate IRQ domain\n");
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return -ENXIO;
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}
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/* Ensures that all non-wakeup IRQs are disabled at suspend */
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bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->parent_wake_irq &&
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of_property_read_bool(np, "wakeup-source")) {
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if (of_property_read_bool(np, "wakeup-source")) {
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priv->parent_wake_irq = platform_get_irq(pdev, 1);
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if (priv->parent_wake_irq < 0) {
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priv->parent_wake_irq = 0;
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@ -387,7 +475,7 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
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if (err < 0) {
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dev_err(dev, "Couldn't request wake IRQ");
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return err;
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goto out_free_domain;
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}
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priv->reboot_notifier.notifier_call =
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@ -396,17 +484,28 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
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}
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}
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if (priv->parent_wake_irq)
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bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
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priv->irq_chip.name = dev_name(dev);
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priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
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priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
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priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
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priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
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priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
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err = gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
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handle_level_irq, IRQ_TYPE_NONE);
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if (err)
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return err;
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gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
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priv->parent_irq, brcmstb_gpio_irq_handler);
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/* Ensures that all non-wakeup IRQs are disabled at suspend */
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priv->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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if (priv->parent_wake_irq)
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priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
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irq_set_chained_handler_and_data(priv->parent_irq,
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brcmstb_gpio_irq_handler, priv);
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return 0;
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out_free_domain:
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irq_domain_remove(priv->irq_domain);
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return err;
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}
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static int brcmstb_gpio_probe(struct platform_device *pdev)
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@ -511,6 +610,8 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
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gc->of_xlate = brcmstb_gpio_of_xlate;
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/* not all ngpio lines are valid, will use bank width later */
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gc->ngpio = MAX_GPIO_PER_BANK;
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if (priv->parent_irq > 0)
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gc->to_irq = brcmstb_gpio_to_irq;
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/*
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* Mask all interrupts by default, since wakeup interrupts may
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@ -526,12 +627,6 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
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}
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gpio_base += gc->ngpio;
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if (priv->parent_irq > 0) {
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err = brcmstb_gpio_irq_setup(pdev, bank);
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if (err)
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goto fail;
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}
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dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
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gc->base, gc->ngpio, bank->width);
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@ -541,6 +636,13 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
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num_banks++;
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}
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priv->num_gpios = gpio_base - priv->gpio_base;
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if (priv->parent_irq > 0) {
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err = brcmstb_gpio_irq_setup(pdev, priv);
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if (err)
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goto fail;
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}
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dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
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num_banks, priv->gpio_base, gpio_base - 1);
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