dma/imx-sdma: convernt to use bit ops
We don't need extra lock, so we use non-atomic bit ops to set/clear bits, merge event_mask0 and event_mask1 into an array, it helps use bit ops. It also fixs the issue: sdmac->event_mask0 = 1 << sdmac->event_id0; sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32); It event_id0 < 32, it shifts negative number. If event_id0 >= 32, it shifts number >= sizeof(int). Both the cases behavior is undefined. Signed-off-by: Richard Zhao <richard.zhao@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Richard Zhao
Vinod Koul
Родитель
b78bd91f47
Коммит
0bbc141302
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@ -20,6 +20,7 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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@ -260,8 +261,8 @@ struct sdma_channel {
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unsigned int pc_from_device, pc_to_device;
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unsigned long flags;
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dma_addr_t per_address;
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u32 event_mask0, event_mask1;
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u32 watermark_level;
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unsigned long event_mask[2];
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unsigned long watermark_level;
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u32 shp_addr, per_addr;
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struct dma_chan chan;
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spinlock_t lock;
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@ -272,7 +273,7 @@ struct sdma_channel {
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unsigned int chn_real_count;
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};
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#define IMX_DMA_SG_LOOP (1 << 0)
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#define IMX_DMA_SG_LOOP BIT(0)
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#define MAX_DMA_CHANNELS 32
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#define MXC_SDMA_DEFAULT_PRIORITY 1
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@ -346,9 +347,9 @@ static const struct of_device_id sdma_dt_ids[] = {
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};
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MODULE_DEVICE_TABLE(of, sdma_dt_ids);
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#define SDMA_H_CONFIG_DSPDMA (1 << 12) /* indicates if the DSPDMA is used */
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#define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
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#define SDMA_H_CONFIG_ACR (1 << 4) /* indicates if AHB freq /core freq = 2 or 1 */
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#define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
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#define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
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#define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
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#define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
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static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
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@ -363,7 +364,7 @@ static int sdma_config_ownership(struct sdma_channel *sdmac,
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{
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struct sdma_engine *sdma = sdmac->sdma;
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int channel = sdmac->channel;
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u32 evt, mcu, dsp;
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unsigned long evt, mcu, dsp;
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if (event_override && mcu_override && dsp_override)
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return -EINVAL;
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@ -373,19 +374,19 @@ static int sdma_config_ownership(struct sdma_channel *sdmac,
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dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
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if (dsp_override)
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dsp &= ~(1 << channel);
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__clear_bit(channel, &dsp);
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else
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dsp |= (1 << channel);
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__set_bit(channel, &dsp);
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if (event_override)
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evt &= ~(1 << channel);
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__clear_bit(channel, &evt);
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else
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evt |= (1 << channel);
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__set_bit(channel, &evt);
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if (mcu_override)
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mcu &= ~(1 << channel);
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__clear_bit(channel, &mcu);
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else
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mcu |= (1 << channel);
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__set_bit(channel, &mcu);
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writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
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writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
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@ -396,7 +397,7 @@ static int sdma_config_ownership(struct sdma_channel *sdmac,
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static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
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{
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writel(1 << channel, sdma->regs + SDMA_H_START);
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writel(BIT(channel), sdma->regs + SDMA_H_START);
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}
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/*
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@ -457,11 +458,11 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
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{
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struct sdma_engine *sdma = sdmac->sdma;
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int channel = sdmac->channel;
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u32 val;
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unsigned long val;
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u32 chnenbl = chnenbl_ofs(sdma, event);
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val = readl_relaxed(sdma->regs + chnenbl);
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val |= (1 << channel);
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__set_bit(channel, &val);
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writel_relaxed(val, sdma->regs + chnenbl);
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}
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@ -470,10 +471,10 @@ static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
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struct sdma_engine *sdma = sdmac->sdma;
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int channel = sdmac->channel;
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u32 chnenbl = chnenbl_ofs(sdma, event);
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u32 val;
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unsigned long val;
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val = readl_relaxed(sdma->regs + chnenbl);
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val &= ~(1 << channel);
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__clear_bit(channel, &val);
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writel_relaxed(val, sdma->regs + chnenbl);
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}
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@ -550,7 +551,7 @@ static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
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static irqreturn_t sdma_int_handler(int irq, void *dev_id)
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{
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struct sdma_engine *sdma = dev_id;
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u32 stat;
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unsigned long stat;
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stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
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writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
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@ -561,7 +562,7 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
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mxc_sdma_handle_channel(sdmac);
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stat &= ~(1 << channel);
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__clear_bit(channel, &stat);
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}
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return IRQ_HANDLED;
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@ -669,11 +670,11 @@ static int sdma_load_context(struct sdma_channel *sdmac)
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return load_address;
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dev_dbg(sdma->dev, "load_address = %d\n", load_address);
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dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
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dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
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dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
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dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
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dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
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dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
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dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
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dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
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mutex_lock(&sdma->channel_0_lock);
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@ -683,8 +684,8 @@ static int sdma_load_context(struct sdma_channel *sdmac)
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/* Send by context the event mask,base address for peripheral
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* and watermark level
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*/
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context->gReg[0] = sdmac->event_mask1;
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context->gReg[1] = sdmac->event_mask0;
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context->gReg[0] = sdmac->event_mask[1];
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context->gReg[1] = sdmac->event_mask[0];
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context->gReg[2] = sdmac->per_addr;
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context->gReg[6] = sdmac->shp_addr;
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context->gReg[7] = sdmac->watermark_level;
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@ -707,7 +708,7 @@ static void sdma_disable_channel(struct sdma_channel *sdmac)
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struct sdma_engine *sdma = sdmac->sdma;
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int channel = sdmac->channel;
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writel_relaxed(1 << channel, sdma->regs + SDMA_H_STATSTOP);
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writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
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sdmac->status = DMA_ERROR;
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}
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@ -717,8 +718,8 @@ static int sdma_config_channel(struct sdma_channel *sdmac)
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sdma_disable_channel(sdmac);
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sdmac->event_mask0 = 0;
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sdmac->event_mask1 = 0;
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sdmac->event_mask[0] = 0;
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sdmac->event_mask[1] = 0;
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sdmac->shp_addr = 0;
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sdmac->per_addr = 0;
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@ -746,15 +747,14 @@ static int sdma_config_channel(struct sdma_channel *sdmac)
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(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
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/* Handle multiple event channels differently */
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if (sdmac->event_id1) {
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sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
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sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
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if (sdmac->event_id1 > 31)
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sdmac->watermark_level |= 1 << 31;
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sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
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__set_bit(31, &sdmac->watermark_level);
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sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
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if (sdmac->event_id0 > 31)
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sdmac->watermark_level |= 1 << 30;
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__set_bit(30, &sdmac->watermark_level);
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} else {
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sdmac->event_mask0 = 1 << sdmac->event_id0;
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sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
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__set_bit(sdmac->event_id0, sdmac->event_mask);
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}
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/* Watermark Level */
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sdmac->watermark_level |= sdmac->watermark_level;
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