MIPS: ath79: Add early printk support for the AR933X SoCs
The AR933X SoCs are using a different UART, thus require different code for early printk support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com> Patchwork: https://patchwork.linux-mips.org/patch/2521/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Gabor Juhos
Ralf Baechle
Родитель
6d1c8fde2d
Коммит
0bd3acdf7d
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@ -1,7 +1,7 @@
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/*
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* Atheros AR71XX/AR724X/AR913X SoC early printk support
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* Atheros AR7XXX/AR9XXX SoC early printk support
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -10,27 +10,85 @@
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/serial_reg.h>
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#include <asm/addrspace.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ar933x_uart.h>
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static inline void prom_wait_thre(void __iomem *base)
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static void (*_prom_putchar) (unsigned char);
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static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
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{
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u32 lsr;
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u32 t;
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do {
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lsr = __raw_readl(base + UART_LSR * 4);
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if (lsr & UART_LSR_THRE)
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t = __raw_readl(reg);
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if ((t & mask) == val)
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break;
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} while (1);
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}
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void prom_putchar(unsigned char ch)
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static void prom_putchar_ar71xx(unsigned char ch)
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{
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void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
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prom_wait_thre(base);
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prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
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__raw_writel(ch, base + UART_TX * 4);
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prom_wait_thre(base);
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prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
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}
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static void prom_putchar_ar933x(unsigned char ch)
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{
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void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
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prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
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AR933X_UART_DATA_TX_CSR);
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__raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
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prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
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AR933X_UART_DATA_TX_CSR);
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}
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static void prom_putchar_dummy(unsigned char ch)
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{
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/* nothing to do */
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}
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static void prom_putchar_init(void)
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{
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void __iomem *base;
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u32 id;
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base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
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id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
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id &= REV_ID_MAJOR_MASK;
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switch (id) {
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case REV_ID_MAJOR_AR71XX:
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case REV_ID_MAJOR_AR7240:
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case REV_ID_MAJOR_AR7241:
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case REV_ID_MAJOR_AR7242:
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case REV_ID_MAJOR_AR913X:
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_prom_putchar = prom_putchar_ar71xx;
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break;
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case REV_ID_MAJOR_AR9330:
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case REV_ID_MAJOR_AR9331:
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_prom_putchar = prom_putchar_ar933x;
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break;
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default:
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_prom_putchar = prom_putchar_dummy;
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break;
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}
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}
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void prom_putchar(unsigned char ch)
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{
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if (!_prom_putchar)
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prom_putchar_init();
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_prom_putchar(ch);
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}
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@ -53,6 +53,9 @@
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#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR913X_WMAC_SIZE 0x30000
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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/*
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* DDR_CTRL block
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*/
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@ -0,0 +1,67 @@
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/*
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* Atheros AR933X UART defines
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __AR933X_UART_H
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#define __AR933X_UART_H
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#define AR933X_UART_REGS_SIZE 20
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#define AR933X_UART_FIFO_SIZE 16
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#define AR933X_UART_DATA_REG 0x00
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#define AR933X_UART_CS_REG 0x04
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#define AR933X_UART_CLOCK_REG 0x08
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#define AR933X_UART_INT_REG 0x0c
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#define AR933X_UART_INT_EN_REG 0x10
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#define AR933X_UART_DATA_TX_RX_MASK 0xff
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#define AR933X_UART_DATA_RX_CSR BIT(8)
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#define AR933X_UART_DATA_TX_CSR BIT(9)
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#define AR933X_UART_CS_PARITY_S 0
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#define AR933X_UART_CS_PARITY_M 0x3
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#define AR933X_UART_CS_PARITY_NONE 0
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#define AR933X_UART_CS_PARITY_ODD 1
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#define AR933X_UART_CS_PARITY_EVEN 2
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#define AR933X_UART_CS_IF_MODE_S 2
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#define AR933X_UART_CS_IF_MODE_M 0x3
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#define AR933X_UART_CS_IF_MODE_NONE 0
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#define AR933X_UART_CS_IF_MODE_DTE 1
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#define AR933X_UART_CS_IF_MODE_DCE 2
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#define AR933X_UART_CS_FLOW_CTRL_S 4
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#define AR933X_UART_CS_FLOW_CTRL_M 0x3
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#define AR933X_UART_CS_DMA_EN BIT(6)
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#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
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#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
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#define AR933X_UART_CS_TX_READY BIT(9)
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#define AR933X_UART_CS_RX_BREAK BIT(10)
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#define AR933X_UART_CS_TX_BREAK BIT(11)
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#define AR933X_UART_CS_HOST_INT BIT(12)
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#define AR933X_UART_CS_HOST_INT_EN BIT(13)
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#define AR933X_UART_CS_TX_BUSY BIT(14)
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#define AR933X_UART_CS_RX_BUSY BIT(15)
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#define AR933X_UART_CLOCK_STEP_M 0xffff
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#define AR933X_UART_CLOCK_SCALE_M 0xfff
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#define AR933X_UART_CLOCK_SCALE_S 16
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#define AR933X_UART_CLOCK_STEP_M 0xffff
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#define AR933X_UART_INT_RX_VALID BIT(0)
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#define AR933X_UART_INT_TX_READY BIT(1)
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#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
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#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
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#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
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#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
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#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
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#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
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#define AR933X_UART_INT_RX_FULL BIT(8)
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#define AR933X_UART_INT_TX_EMPTY BIT(9)
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#define AR933X_UART_INT_ALLINTS 0x3ff
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#endif /* __AR933X_UART_H */
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