drm/amdgpu: split gfx8 gpu init into sw and hw parts
Calculate the driver state in sw_init and program the registers in hw init. Acked-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
Родитель
1c5dc33514
Коммит
0bde3a95ea
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@ -903,6 +903,191 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
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return 0;
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}
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static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
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{
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u32 gb_addr_config;
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u32 mc_shared_chmap, mc_arb_ramcfg;
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u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
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u32 tmp;
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switch (adev->asic_type) {
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case CHIP_TOPAZ:
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adev->gfx.config.max_shader_engines = 1;
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adev->gfx.config.max_tile_pipes = 2;
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adev->gfx.config.max_cu_per_sh = 6;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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adev->gfx.config.max_texture_channel_caches = 2;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
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break;
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case CHIP_FIJI:
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adev->gfx.config.max_shader_engines = 4;
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adev->gfx.config.max_tile_pipes = 16;
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adev->gfx.config.max_cu_per_sh = 16;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 4;
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adev->gfx.config.max_texture_channel_caches = 8;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
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break;
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case CHIP_TONGA:
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adev->gfx.config.max_shader_engines = 4;
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adev->gfx.config.max_tile_pipes = 8;
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adev->gfx.config.max_cu_per_sh = 8;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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adev->gfx.config.max_texture_channel_caches = 8;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
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break;
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case CHIP_CARRIZO:
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adev->gfx.config.max_shader_engines = 1;
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adev->gfx.config.max_tile_pipes = 2;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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switch (adev->pdev->revision) {
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case 0xc4:
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case 0x84:
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case 0xc8:
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case 0xcc:
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/* B10 */
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adev->gfx.config.max_cu_per_sh = 8;
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break;
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case 0xc5:
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case 0x81:
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case 0x85:
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case 0xc9:
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case 0xcd:
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/* B8 */
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adev->gfx.config.max_cu_per_sh = 6;
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break;
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case 0xc6:
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case 0xca:
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case 0xce:
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/* B6 */
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adev->gfx.config.max_cu_per_sh = 6;
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break;
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case 0xc7:
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case 0x87:
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case 0xcb:
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default:
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/* B4 */
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adev->gfx.config.max_cu_per_sh = 4;
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break;
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}
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adev->gfx.config.max_texture_channel_caches = 2;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
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break;
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default:
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adev->gfx.config.max_shader_engines = 2;
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adev->gfx.config.max_tile_pipes = 4;
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adev->gfx.config.max_cu_per_sh = 2;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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adev->gfx.config.max_texture_channel_caches = 4;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
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break;
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}
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mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
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adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
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mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
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adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
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adev->gfx.config.mem_max_burst_length_bytes = 256;
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if (adev->flags & AMD_IS_APU) {
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/* Get memory bank mapping mode. */
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tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
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dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
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dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
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tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
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dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
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dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
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/* Validate settings in case only one DIMM installed. */
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if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
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dimm00_addr_map = 0;
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if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
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dimm01_addr_map = 0;
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if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
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dimm10_addr_map = 0;
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if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
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dimm11_addr_map = 0;
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/* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
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/* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
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if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
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adev->gfx.config.mem_row_size_in_kb = 2;
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else
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adev->gfx.config.mem_row_size_in_kb = 1;
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} else {
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tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
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adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
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if (adev->gfx.config.mem_row_size_in_kb > 4)
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adev->gfx.config.mem_row_size_in_kb = 4;
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}
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adev->gfx.config.shader_engine_tile_size = 32;
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adev->gfx.config.num_gpus = 1;
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adev->gfx.config.multi_gpu_tile_size = 64;
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/* fix up row size */
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switch (adev->gfx.config.mem_row_size_in_kb) {
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case 1:
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default:
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gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
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break;
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case 2:
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gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
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break;
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case 4:
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gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
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break;
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}
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adev->gfx.config.gb_addr_config = gb_addr_config;
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}
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static int gfx_v8_0_sw_init(void *handle)
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{
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int i, r;
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@ -1010,6 +1195,8 @@ static int gfx_v8_0_sw_init(void *handle)
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adev->gfx.ce_ram_size = 0x8000;
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gfx_v8_0_gpu_early_init(adev);
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return 0;
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}
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@ -2043,203 +2230,23 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
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static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
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{
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u32 gb_addr_config;
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u32 mc_shared_chmap, mc_arb_ramcfg;
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u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
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u32 tmp;
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int i;
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switch (adev->asic_type) {
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case CHIP_TOPAZ:
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adev->gfx.config.max_shader_engines = 1;
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adev->gfx.config.max_tile_pipes = 2;
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adev->gfx.config.max_cu_per_sh = 6;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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adev->gfx.config.max_texture_channel_caches = 2;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
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break;
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case CHIP_FIJI:
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adev->gfx.config.max_shader_engines = 4;
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adev->gfx.config.max_tile_pipes = 16;
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adev->gfx.config.max_cu_per_sh = 16;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 4;
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adev->gfx.config.max_texture_channel_caches = 8;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
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break;
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case CHIP_TONGA:
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adev->gfx.config.max_shader_engines = 4;
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adev->gfx.config.max_tile_pipes = 8;
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adev->gfx.config.max_cu_per_sh = 8;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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adev->gfx.config.max_texture_channel_caches = 8;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
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break;
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case CHIP_CARRIZO:
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adev->gfx.config.max_shader_engines = 1;
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adev->gfx.config.max_tile_pipes = 2;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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switch (adev->pdev->revision) {
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case 0xc4:
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case 0x84:
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case 0xc8:
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case 0xcc:
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/* B10 */
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adev->gfx.config.max_cu_per_sh = 8;
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break;
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case 0xc5:
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case 0x81:
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case 0x85:
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case 0xc9:
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case 0xcd:
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/* B8 */
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adev->gfx.config.max_cu_per_sh = 6;
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break;
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case 0xc6:
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case 0xca:
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case 0xce:
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/* B6 */
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adev->gfx.config.max_cu_per_sh = 6;
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break;
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case 0xc7:
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case 0x87:
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case 0xcb:
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default:
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/* B4 */
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adev->gfx.config.max_cu_per_sh = 4;
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break;
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}
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adev->gfx.config.max_texture_channel_caches = 2;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
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break;
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default:
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adev->gfx.config.max_shader_engines = 2;
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adev->gfx.config.max_tile_pipes = 4;
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adev->gfx.config.max_cu_per_sh = 2;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 2;
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adev->gfx.config.max_texture_channel_caches = 4;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
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adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
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adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
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adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
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break;
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}
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tmp = RREG32(mmGRBM_CNTL);
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tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
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WREG32(mmGRBM_CNTL, tmp);
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mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
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adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
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mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
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adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
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adev->gfx.config.mem_max_burst_length_bytes = 256;
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if (adev->flags & AMD_IS_APU) {
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/* Get memory bank mapping mode. */
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tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
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dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
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dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
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tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
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dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
|
||||
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
|
||||
|
||||
/* Validate settings in case only one DIMM installed. */
|
||||
if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
|
||||
dimm00_addr_map = 0;
|
||||
if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
|
||||
dimm01_addr_map = 0;
|
||||
if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
|
||||
dimm10_addr_map = 0;
|
||||
if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
|
||||
dimm11_addr_map = 0;
|
||||
|
||||
/* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
|
||||
/* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
|
||||
if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
|
||||
adev->gfx.config.mem_row_size_in_kb = 2;
|
||||
else
|
||||
adev->gfx.config.mem_row_size_in_kb = 1;
|
||||
} else {
|
||||
tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
|
||||
adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
|
||||
if (adev->gfx.config.mem_row_size_in_kb > 4)
|
||||
adev->gfx.config.mem_row_size_in_kb = 4;
|
||||
}
|
||||
|
||||
adev->gfx.config.shader_engine_tile_size = 32;
|
||||
adev->gfx.config.num_gpus = 1;
|
||||
adev->gfx.config.multi_gpu_tile_size = 64;
|
||||
|
||||
/* fix up row size */
|
||||
switch (adev->gfx.config.mem_row_size_in_kb) {
|
||||
case 1:
|
||||
default:
|
||||
gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
|
||||
break;
|
||||
case 2:
|
||||
gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
|
||||
break;
|
||||
case 4:
|
||||
gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
|
||||
break;
|
||||
}
|
||||
adev->gfx.config.gb_addr_config = gb_addr_config;
|
||||
|
||||
WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
|
||||
WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
|
||||
WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
|
||||
WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
|
||||
WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
|
||||
gb_addr_config & 0x70);
|
||||
adev->gfx.config.gb_addr_config & 0x70);
|
||||
WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
|
||||
gb_addr_config & 0x70);
|
||||
WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
|
||||
adev->gfx.config.gb_addr_config & 0x70);
|
||||
WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
|
||||
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
|
||||
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
|
||||
|
||||
gfx_v8_0_tiling_mode_table_init(adev);
|
||||
|
||||
|
|
@ -2256,13 +2263,13 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
|
|||
if (i == 0) {
|
||||
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
|
||||
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
|
||||
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
|
||||
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
|
||||
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
|
||||
WREG32(mmSH_MEM_CONFIG, tmp);
|
||||
} else {
|
||||
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
|
||||
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
|
||||
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
|
||||
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
|
||||
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
|
||||
WREG32(mmSH_MEM_CONFIG, tmp);
|
||||
}
|
||||
|
|
|
|||
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