drm/amdgpu: used cached pcie gen info for SI (v2)
Rather than querying it every time we need it. Also fixes a crash in VM pass through if there is no root bridge because the cached value fetch already checks this properly. v2: fix includes Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
This commit is contained in:
Alex Deucher
Родитель
9c5c71bbed
Коммит
0bf6718537
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@ -31,6 +31,7 @@
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#include "amdgpu_uvd.h"
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#include "amdgpu_vce.h"
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#include "atom.h"
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#include "amd_pcie.h"
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#include "amdgpu_powerplay.h"
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#include "sid.h"
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#include "si_ih.h"
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@ -1484,8 +1485,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
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{
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struct pci_dev *root = adev->pdev->bus->self;
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int bridge_pos, gpu_pos;
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u32 speed_cntl, mask, current_data_rate;
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int ret, i;
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u32 speed_cntl, current_data_rate;
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int i;
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u16 tmp16;
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if (pci_is_root_bus(adev->pdev->bus))
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@ -1497,23 +1498,20 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
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if (adev->flags & AMD_IS_APU)
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return;
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ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
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if (ret != 0)
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return;
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if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
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if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
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CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
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return;
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speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
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current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
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LC_CURRENT_DATA_RATE_SHIFT;
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if (mask & DRM_PCIE_SPEED_80) {
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if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
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if (current_data_rate == 2) {
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DRM_INFO("PCIE gen 3 link speeds already enabled\n");
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return;
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}
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DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
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} else if (mask & DRM_PCIE_SPEED_50) {
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} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
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if (current_data_rate == 1) {
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DRM_INFO("PCIE gen 2 link speeds already enabled\n");
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return;
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@ -1529,7 +1527,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
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if (!gpu_pos)
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return;
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if (mask & DRM_PCIE_SPEED_80) {
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if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
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if (current_data_rate != 2) {
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u16 bridge_cfg, gpu_cfg;
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u16 bridge_cfg2, gpu_cfg2;
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@ -1612,9 +1610,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
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pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
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tmp16 &= ~0xf;
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if (mask & DRM_PCIE_SPEED_80)
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if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
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tmp16 |= 3;
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else if (mask & DRM_PCIE_SPEED_50)
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else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
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tmp16 |= 2;
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else
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tmp16 |= 1;
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@ -26,6 +26,7 @@
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#include "amdgpu_pm.h"
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#include "amdgpu_dpm.h"
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#include "amdgpu_atombios.h"
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#include "amd_pcie.h"
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#include "sid.h"
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#include "r600_dpm.h"
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#include "si_dpm.h"
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@ -3331,29 +3332,6 @@ static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
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}
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}
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static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
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u32 sys_mask,
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enum amdgpu_pcie_gen asic_gen,
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enum amdgpu_pcie_gen default_gen)
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{
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switch (asic_gen) {
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case AMDGPU_PCIE_GEN1:
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return AMDGPU_PCIE_GEN1;
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case AMDGPU_PCIE_GEN2:
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return AMDGPU_PCIE_GEN2;
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case AMDGPU_PCIE_GEN3:
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return AMDGPU_PCIE_GEN3;
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default:
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if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
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return AMDGPU_PCIE_GEN3;
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else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
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return AMDGPU_PCIE_GEN2;
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else
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return AMDGPU_PCIE_GEN1;
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}
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return AMDGPU_PCIE_GEN1;
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}
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static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
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u32 *p, u32 *u)
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{
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@ -5028,10 +5006,11 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
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table->ACPIState.levels[0].vddc.index,
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&table->ACPIState.levels[0].std_vddc);
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}
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table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
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si_pi->sys_pcie_mask,
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si_pi->boot_pcie_gen,
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AMDGPU_PCIE_GEN1);
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table->ACPIState.levels[0].gen2PCIE =
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(u8)amdgpu_get_pcie_gen_support(adev,
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si_pi->sys_pcie_mask,
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si_pi->boot_pcie_gen,
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AMDGPU_PCIE_GEN1);
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if (si_pi->vddc_phase_shed_control)
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si_populate_phase_shedding_value(adev,
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@ -7168,10 +7147,10 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
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pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
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pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
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pl->flags = le32_to_cpu(clock_info->si.ulFlags);
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pl->pcie_gen = r600_get_pcie_gen_support(adev,
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si_pi->sys_pcie_mask,
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si_pi->boot_pcie_gen,
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clock_info->si.ucPCIEGen);
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pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
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si_pi->sys_pcie_mask,
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si_pi->boot_pcie_gen,
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clock_info->si.ucPCIEGen);
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/* patch up vddc if necessary */
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ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
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@ -7326,7 +7305,6 @@ static int si_dpm_init(struct amdgpu_device *adev)
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struct si_power_info *si_pi;
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struct atom_clock_dividers dividers;
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int ret;
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u32 mask;
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si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
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if (si_pi == NULL)
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@ -7336,11 +7314,9 @@ static int si_dpm_init(struct amdgpu_device *adev)
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eg_pi = &ni_pi->eg;
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pi = &eg_pi->rv7xx;
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ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
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if (ret)
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si_pi->sys_pcie_mask = 0;
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else
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si_pi->sys_pcie_mask = mask;
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si_pi->sys_pcie_mask =
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(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
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CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
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si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
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si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
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