drm/amdgpu: remove the exclusive lock
Finally getting rid of it. Signed-off-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Родитель
b7e4dad3e1
Коммит
0c418f1010
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@ -1955,7 +1955,6 @@ struct amdgpu_device {
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struct device *dev;
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struct drm_device *ddev;
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struct pci_dev *pdev;
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struct rw_semaphore exclusive_lock;
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/* ASIC */
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enum amd_asic_type asic_type;
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@ -831,11 +831,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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bool reserved_buffers = false;
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int i, r;
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down_read(&adev->exclusive_lock);
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if (!adev->accel_working) {
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up_read(&adev->exclusive_lock);
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if (!adev->accel_working)
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return -EBUSY;
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}
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parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
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if (!parser)
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@ -843,8 +840,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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r = amdgpu_cs_parser_init(parser, data);
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if (r) {
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DRM_ERROR("Failed to initialize parser !\n");
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kfree(parser);
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up_read(&adev->exclusive_lock);
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amdgpu_cs_parser_fini(parser, r, false);
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r = amdgpu_cs_handle_lockup(adev, r);
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return r;
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}
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@ -915,14 +911,12 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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mutex_unlock(&job->job_lock);
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amdgpu_cs_parser_fini_late(parser);
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up_read(&adev->exclusive_lock);
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return 0;
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}
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cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
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out:
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amdgpu_cs_parser_fini(parser, r, reserved_buffers);
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up_read(&adev->exclusive_lock);
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r = amdgpu_cs_handle_lockup(adev, r);
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return r;
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}
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@ -1418,7 +1418,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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mutex_init(&adev->gfx.gpu_clock_mutex);
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mutex_init(&adev->srbm_mutex);
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mutex_init(&adev->grbm_idx_mutex);
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init_rwsem(&adev->exclusive_lock);
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mutex_init(&adev->mn_lock);
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hash_init(adev->mn_hash);
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@ -1814,8 +1813,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
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int i, r;
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int resched;
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down_write(&adev->exclusive_lock);
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atomic_inc(&adev->gpu_reset_counter);
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/* block TTM */
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@ -1879,7 +1876,6 @@ retry:
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dev_info(adev->dev, "GPU reset failed\n");
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}
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up_write(&adev->exclusive_lock);
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return r;
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}
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@ -47,11 +47,8 @@ static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
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fence = to_amdgpu_fence(*f);
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if (fence) {
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r = fence_wait(&fence->base, false);
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if (r == -EDEADLK) {
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up_read(&adev->exclusive_lock);
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if (r == -EDEADLK)
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r = amdgpu_gpu_reset(adev);
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down_read(&adev->exclusive_lock);
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}
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} else
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r = fence_wait(*f, false);
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@ -77,7 +74,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
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unsigned long flags;
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unsigned i;
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down_read(&adev->exclusive_lock);
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amdgpu_flip_wait_fence(adev, &work->excl);
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for (i = 0; i < work->shared_count; ++i)
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amdgpu_flip_wait_fence(adev, &work->shared[i]);
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@ -93,7 +89,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
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amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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up_read(&adev->exclusive_lock);
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}
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/*
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@ -260,16 +260,8 @@ static void amdgpu_fence_check_lockup(struct work_struct *work)
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lockup_work.work);
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ring = fence_drv->ring;
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if (!down_read_trylock(&ring->adev->exclusive_lock)) {
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/* just reschedule the check if a reset is going on */
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amdgpu_fence_schedule_check(ring);
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return;
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}
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if (amdgpu_fence_activity(ring)) {
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if (amdgpu_fence_activity(ring))
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wake_up_all(&ring->fence_drv.fence_queue);
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}
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up_read(&ring->adev->exclusive_lock);
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}
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/**
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@ -317,18 +309,15 @@ static bool amdgpu_fence_is_signaled(struct fence *f)
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{
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struct amdgpu_fence *fence = to_amdgpu_fence(f);
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struct amdgpu_ring *ring = fence->ring;
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struct amdgpu_device *adev = ring->adev;
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if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
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return true;
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if (down_read_trylock(&adev->exclusive_lock)) {
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amdgpu_fence_process(ring);
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up_read(&adev->exclusive_lock);
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amdgpu_fence_process(ring);
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if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
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return true;
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if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
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return true;
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}
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return false;
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}
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@ -181,7 +181,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
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bool kernel = false;
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int r;
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down_read(&adev->exclusive_lock);
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/* create a gem object to contain this object in */
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if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
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AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
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@ -214,11 +213,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
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memset(args, 0, sizeof(*args));
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args->out.handle = handle;
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up_read(&adev->exclusive_lock);
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return 0;
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error_unlock:
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up_read(&adev->exclusive_lock);
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r = amdgpu_gem_handle_lockup(adev, r);
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return r;
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}
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@ -250,8 +247,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
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return -EACCES;
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}
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down_read(&adev->exclusive_lock);
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/* create a gem object to contain this object in */
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r = amdgpu_gem_object_create(adev, args->size, 0,
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AMDGPU_GEM_DOMAIN_CPU, 0,
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@ -293,14 +288,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
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goto handle_lockup;
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args->handle = handle;
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up_read(&adev->exclusive_lock);
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return 0;
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release_object:
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drm_gem_object_unreference_unlocked(gobj);
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handle_lockup:
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up_read(&adev->exclusive_lock);
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r = amdgpu_gem_handle_lockup(adev, r);
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return r;
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