ASoC: rt5682: Enable PLL2 function
Enable RT5682 PLL2 function to implement the more complex frequency conversion. Signed-off-by: derek.fang <derek.fang@realtek.com> Link: https://lore.kernel.org/r/1581577510-1807-1-git-send-email-derek.fang@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
derek.fang
Mark Brown
Родитель
ff0035e4c2
Коммит
0c48a65394
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@ -64,9 +64,9 @@ struct rt5682_priv {
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int bclk[RT5682_AIFS];
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int master[RT5682_AIFS];
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int pll_src;
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int pll_in;
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int pll_out;
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int pll_src[RT5682_PLLS];
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int pll_in[RT5682_PLLS];
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int pll_out[RT5682_PLLS];
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int jack_type;
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};
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@ -75,6 +75,7 @@ static const struct reg_sequence patch_list[] = {
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{RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
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{RT5682_DAC_ADC_DIG_VOL1, 0xa020},
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{RT5682_I2C_CTRL, 0x000f},
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{RT5682_PLL2_INTERNAL, 0x8266},
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};
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static const struct reg_default rt5682_reg[] = {
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@ -222,7 +223,7 @@ static const struct reg_default rt5682_reg[] = {
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{0x0148, 0x0000},
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{0x0149, 0x0000},
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{0x0150, 0x79a1},
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{0x0151, 0x0000},
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{0x0156, 0xaaaa},
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{0x0160, 0x4ec0},
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{0x0161, 0x0080},
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{0x0162, 0x0200},
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@ -928,10 +929,10 @@ static int rt5682_headset_detect(struct snd_soc_component *component,
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RT5682_PWR_VREF2 | RT5682_PWR_MB,
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RT5682_PWR_VREF2 | RT5682_PWR_MB);
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snd_soc_component_update_bits(component,
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RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
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RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
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usleep_range(15000, 20000);
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snd_soc_component_update_bits(component,
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RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
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RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
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snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
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RT5682_PWR_CBJ, RT5682_PWR_CBJ);
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@ -1298,6 +1299,21 @@ static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
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return 0;
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}
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static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
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struct snd_soc_dapm_widget *sink)
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{
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unsigned int val;
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struct snd_soc_component *component =
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snd_soc_dapm_to_component(w->dapm);
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val = snd_soc_component_read32(component, RT5682_GLB_CLK);
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val &= RT5682_SCLK_SRC_MASK;
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if (val == RT5682_SCLK_SRC_PLL2)
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return 1;
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else
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return 0;
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}
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static int is_using_asrc(struct snd_soc_dapm_widget *w,
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struct snd_soc_dapm_widget *sink)
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{
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@ -1612,9 +1628,11 @@ static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
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SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
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0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
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0, NULL, 0),
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0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
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SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
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rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
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SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
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NULL, 0),
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/* ASRC */
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SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
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@ -1796,7 +1814,11 @@ static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
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static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
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/*PLL*/
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{"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
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{"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
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{"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
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{"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
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{"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
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{"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
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/*ASRC*/
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{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
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@ -2053,8 +2075,10 @@ static int rt5682_hw_params(struct snd_pcm_substream *substream,
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RT5682_I2S1_DL_MASK, len_1);
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if (rt5682->master[RT5682_AIF1]) {
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snd_soc_component_update_bits(component,
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RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
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pre_div << RT5682_I2S_M_DIV_SFT);
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RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
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RT5682_I2S_CLK_SRC_MASK,
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pre_div << RT5682_I2S_M_DIV_SFT |
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(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
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}
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if (params_channels(params) == 1) /* mono mode */
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snd_soc_component_update_bits(component,
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@ -2227,61 +2251,157 @@ static int rt5682_set_component_pll(struct snd_soc_component *component,
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unsigned int freq_out)
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{
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struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
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struct rl6231_pll_code pll_code;
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struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
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unsigned int pll2_fout1;
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int ret;
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if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
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freq_out == rt5682->pll_out)
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if (source == rt5682->pll_src[pll_id] &&
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freq_in == rt5682->pll_in[pll_id] &&
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freq_out == rt5682->pll_out[pll_id])
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return 0;
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if (!freq_in || !freq_out) {
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dev_dbg(component->dev, "PLL disabled\n");
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rt5682->pll_in = 0;
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rt5682->pll_out = 0;
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rt5682->pll_in[pll_id] = 0;
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rt5682->pll_out[pll_id] = 0;
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snd_soc_component_update_bits(component, RT5682_GLB_CLK,
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RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
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return 0;
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}
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switch (source) {
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case RT5682_PLL1_S_MCLK:
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snd_soc_component_update_bits(component, RT5682_GLB_CLK,
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RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
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break;
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case RT5682_PLL1_S_BCLK1:
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snd_soc_component_update_bits(component, RT5682_GLB_CLK,
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RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
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break;
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default:
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dev_err(component->dev, "Unknown PLL Source %d\n", source);
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return -EINVAL;
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if (pll_id == RT5682_PLL2) {
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switch (source) {
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case RT5682_PLL2_S_MCLK:
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snd_soc_component_update_bits(component,
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RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
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RT5682_PLL2_SRC_MCLK);
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break;
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default:
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dev_err(component->dev, "Unknown PLL2 Source %d\n",
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source);
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return -EINVAL;
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}
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/**
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* PLL2 concatenates 2 PLL units.
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* We suggest the Fout of the front PLL is 3.84MHz.
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*/
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pll2_fout1 = 3840000;
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ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
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if (ret < 0) {
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dev_err(component->dev, "Unsupport input clock %d\n",
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freq_in);
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return ret;
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}
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dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
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freq_in, pll2_fout1,
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pll2f_code.m_bp,
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(pll2f_code.m_bp ? 0 : pll2f_code.m_code),
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pll2f_code.n_code, pll2f_code.k_code);
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ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
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if (ret < 0) {
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dev_err(component->dev, "Unsupport input clock %d\n",
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pll2_fout1);
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return ret;
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}
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dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
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pll2_fout1, freq_out,
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pll2b_code.m_bp,
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(pll2b_code.m_bp ? 0 : pll2b_code.m_code),
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pll2b_code.n_code, pll2b_code.k_code);
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snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
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pll2f_code.k_code << RT5682_PLL2F_K_SFT |
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pll2b_code.k_code << RT5682_PLL2B_K_SFT |
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pll2b_code.m_code);
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snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
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pll2f_code.m_code << RT5682_PLL2F_M_SFT |
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pll2b_code.n_code);
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snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
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pll2f_code.n_code << RT5682_PLL2F_N_SFT);
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snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
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RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
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(pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
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(pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
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0xf);
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} else {
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switch (source) {
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case RT5682_PLL1_S_MCLK:
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snd_soc_component_update_bits(component,
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RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
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RT5682_PLL1_SRC_MCLK);
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break;
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case RT5682_PLL1_S_BCLK1:
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snd_soc_component_update_bits(component,
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RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
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RT5682_PLL1_SRC_BCLK1);
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break;
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default:
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dev_err(component->dev, "Unknown PLL1 Source %d\n",
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source);
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return -EINVAL;
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}
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ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
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if (ret < 0) {
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dev_err(component->dev, "Unsupport input clock %d\n",
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freq_in);
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return ret;
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}
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dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
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pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
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pll_code.n_code, pll_code.k_code);
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snd_soc_component_write(component, RT5682_PLL_CTRL_1,
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pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
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snd_soc_component_write(component, RT5682_PLL_CTRL_2,
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(pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
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pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
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}
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ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
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if (ret < 0) {
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dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
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return ret;
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}
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dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
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pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
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pll_code.n_code, pll_code.k_code);
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snd_soc_component_write(component, RT5682_PLL_CTRL_1,
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pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
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snd_soc_component_write(component, RT5682_PLL_CTRL_2,
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(pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
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pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
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rt5682->pll_in = freq_in;
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rt5682->pll_out = freq_out;
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rt5682->pll_src = source;
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rt5682->pll_in[pll_id] = freq_in;
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rt5682->pll_out[pll_id] = freq_out;
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rt5682->pll_src[pll_id] = source;
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return 0;
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}
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static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
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static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
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{
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struct snd_soc_component *component = dai->component;
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struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
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rt5682->bclk[dai->id] = ratio;
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switch (ratio) {
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case 256:
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snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
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RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
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break;
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case 128:
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snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
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RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
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break;
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case 64:
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snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
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RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
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break;
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case 32:
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snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
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RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
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break;
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default:
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dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
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return -EINVAL;
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}
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return 0;
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}
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static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
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{
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struct snd_soc_component *component = dai->component;
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struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
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@ -2300,7 +2420,7 @@ static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
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RT5682_I2S2_BCLK_MS2_32);
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break;
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default:
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dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
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dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
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return -EINVAL;
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}
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@ -2389,12 +2509,13 @@ static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
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.hw_params = rt5682_hw_params,
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.set_fmt = rt5682_set_dai_fmt,
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.set_tdm_slot = rt5682_set_tdm_slot,
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.set_bclk_ratio = rt5682_set_bclk1_ratio,
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};
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static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
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.hw_params = rt5682_hw_params,
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.set_fmt = rt5682_set_dai_fmt,
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.set_bclk_ratio = rt5682_set_bclk_ratio,
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.set_bclk_ratio = rt5682_set_bclk2_ratio,
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};
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static struct snd_soc_dai_driver rt5682_dai[] = {
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@ -177,7 +177,7 @@
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#define RT5682_TEST_MODE_CTRL_4 0x0148
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#define RT5682_TEST_MODE_CTRL_5 0x0149
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#define RT5682_PLL1_INTERNAL 0x0150
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#define RT5682_PLL2_INTERNAL 0x0151
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#define RT5682_PLL2_INTERNAL 0x0156
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#define RT5682_STO_NG2_CTRL_1 0x0160
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#define RT5682_STO_NG2_CTRL_2 0x0161
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#define RT5682_STO_NG2_CTRL_3 0x0162
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@ -738,7 +738,7 @@
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#define RT5682_ADC_OSR_D_24 (0x7 << 12)
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#define RT5682_ADC_OSR_D_32 (0x8 << 12)
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#define RT5682_ADC_OSR_D_48 (0x9 << 12)
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#define RT5682_I2S_M_DIV_MASK (0xf << 12)
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#define RT5682_I2S_M_DIV_MASK (0xf << 8)
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#define RT5682_I2S_M_DIV_SFT 8
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#define RT5682_I2S_M_D_1 (0x0 << 8)
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#define RT5682_I2S_M_D_2 (0x1 << 8)
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@ -820,6 +820,12 @@
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#define RT5682_TDM_DF_PCM_B (0x3 << 11)
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#define RT5682_TDM_DF_PCM_A_N (0x6 << 11)
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#define RT5682_TDM_DF_PCM_B_N (0x7 << 11)
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#define RT5682_TDM_BCLK_MS1_MASK (0x3 << 9)
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#define RT5682_TDM_BCLK_MS1_SFT 9
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#define RT5682_TDM_BCLK_MS1_32 (0x0 << 9)
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#define RT5682_TDM_BCLK_MS1_64 (0x1 << 9)
|
||||
#define RT5682_TDM_BCLK_MS1_128 (0x2 << 9)
|
||||
#define RT5682_TDM_BCLK_MS1_256 (0x3 << 9)
|
||||
#define RT5682_TDM_CL_MASK (0x3 << 4)
|
||||
#define RT5682_TDM_CL_16 (0x0 << 4)
|
||||
#define RT5682_TDM_CL_20 (0x1 << 4)
|
||||
|
|
@ -1049,6 +1055,28 @@
|
|||
#define RT5682_PWR_CLK1M_PD (0x0 << 8)
|
||||
#define RT5682_PWR_CLK1M_PU (0x1 << 8)
|
||||
|
||||
/* PLL2 M/N/K Code Control 1 (0x009b) */
|
||||
#define RT5682_PLL2F_K_MASK (0x1f << 8)
|
||||
#define RT5682_PLL2F_K_SFT 8
|
||||
#define RT5682_PLL2B_K_MASK (0xf << 4)
|
||||
#define RT5682_PLL2B_K_SFT 4
|
||||
#define RT5682_PLL2B_M_MASK (0xf << 0)
|
||||
|
||||
/* PLL2 M/N/K Code Control 2 (0x009c) */
|
||||
#define RT5682_PLL2F_M_MASK (0x3f << 8)
|
||||
#define RT5682_PLL2F_M_SFT 8
|
||||
#define RT5682_PLL2B_N_MASK (0x3f << 0)
|
||||
|
||||
/* PLL2 M/N/K Code Control 2 (0x009d) */
|
||||
#define RT5682_PLL2F_N_MASK (0x7f << 8)
|
||||
#define RT5682_PLL2F_N_SFT 8
|
||||
|
||||
/* PLL2 M/N/K Code Control 2 (0x009e) */
|
||||
#define RT5682_PLL2B_M_BP_MASK (0x1 << 11)
|
||||
#define RT5682_PLL2B_M_BP_SFT 11
|
||||
#define RT5682_PLL2F_M_BP_MASK (0x1 << 7)
|
||||
#define RT5682_PLL2F_M_BP_SFT 7
|
||||
|
||||
/* RC Clock Control (0x009f) */
|
||||
#define RT5682_POW_IRQ (0x1 << 15)
|
||||
#define RT5682_POW_JDH (0x1 << 14)
|
||||
|
|
@ -1315,6 +1343,13 @@ enum {
|
|||
RT5682_PLL1_S_MCLK,
|
||||
RT5682_PLL1_S_BCLK1,
|
||||
RT5682_PLL1_S_RCCLK,
|
||||
RT5682_PLL2_S_MCLK,
|
||||
};
|
||||
|
||||
enum {
|
||||
RT5682_PLL1,
|
||||
RT5682_PLL2,
|
||||
RT5682_PLLS,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
|
|||
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