diff --git a/MAINTAINERS b/MAINTAINERS index 66662b80e711..5affae6e99b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2377,6 +2377,7 @@ M: Brian Norris M: Gregory Fong M: Florian Fainelli L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: bcm-kernel-feedback-list@broadcom.com T: git git://github.com/broadcom/stblinux.git S: Maintained F: arch/arm/mach-bcm/*brcmstb* @@ -2450,7 +2451,7 @@ N: bcm88312 BROADCOM BRCMSTB GPIO DRIVER M: Gregory Fong -L: bcm-kernel-feedback-list@broadcom.com> +L: bcm-kernel-feedback-list@broadcom.com S: Supported F: drivers/gpio/gpio-brcmstb.c F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi index ef1e8e7a6cc6..26001585673a 100644 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -4,18 +4,41 @@ * published by the Free Software Foundation. */ -&scm_clocks { - - tclkin_ck: tclkin_ck { +&pllss_clocks { + timer1_fck: timer1_fck { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <3>; + reg = <0x2e0>; }; + timer2_fck: timer2_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <6>; + reg = <0x2e0>; + }; + + sysclk18_ck: sysclk18_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&rtcosc_ck>, <&rtcdivider_ck>; + ti,bit-shift = <0>; + reg = <0x02f0>; + }; +}; + +&scm_clocks { devosc_ck: devosc_ck { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; + compatible = "ti,mux-clock"; + clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; + ti,bit-shift = <21>; + reg = <0x0040>; }; /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */ @@ -25,6 +48,32 @@ clock-frequency = <27000000>; }; + /* Optional 32768Hz crystal or clock on RTCOSC pins */ + rtcosc_ck: rtcosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + /* Optional external clock on TCLKIN pin, set rate in baord dts file */ + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + virt_20000000_ck: virt_20000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + mpu_ck: mpu_ck { #clock-cells = <0>; compatible = "fixed-clock"; @@ -49,12 +98,6 @@ clock-frequency = <48000000>; }; - sysclk18_ck: sysclk18_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -69,7 +112,31 @@ }; -&pllss_clocks { +&prcm_clocks { + osc_src_ck: osc_src_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&devosc_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mpu_clksrc_ck: mpu_clksrc_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&devosc_ck>, <&rtcdivider_ck>; + ti,bit-shift = <0>; + reg = <0x0040>; + }; + + /* Fixed divider clock 0.0016384 * devosc */ + rtcdivider_ck: rtcdivider_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&devosc_ck>; + clock-mult = <128>; + clock-div = <78125>; + }; aud_clkin0_ck: aud_clkin0_ck { #clock-cells = <0>; @@ -88,22 +155,4 @@ compatible = "fixed-clock"; clock-frequency = <20000000>; }; - - timer1_mux_ck: timer1_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <3>; - reg = <0x2e0>; - }; - - timer2_mux_ck: timer2_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <6>; - reg = <0x2e0>; - }; }; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 7988b42e5764..09a8d88bde23 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -58,8 +58,10 @@ ti,hwmods = "l3_main"; /* - * See TRM "Table 1-317. L4LS Instance Summary", just deduct - * 0x1000 from the 1-317 addresses to get the device address + * See TRM "Table 1-317. L4LS Instance Summary" for hints. + * It shows the module target agent registers though, so the + * actual device is typically 0x1000 before the target agent + * except in cases where the module is larger than 0x1000. */ l4ls: l4ls@48000000 { compatible = "ti,dm814-l4ls", "simple-bus"; @@ -183,10 +185,10 @@ control: control@140000 { compatible = "ti,dm814-scm", "simple-bus"; - reg = <0x140000 0x16d000>; + reg = <0x140000 0x20000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x160000 0x16d000>; + ranges = <0 0x140000 0x20000>; scm_conf: scm_conf@0 { compatible = "syscon"; @@ -203,19 +205,30 @@ }; }; + /* + * Note that silicon revision 2.1 and older + * require input enabled (bit 18 set) for all + * 3.3V I/Os to avoid cumulative hardware damage. + * For more info, see errata advisory 2.1.87. + * We leave bit 18 out of function-mask and rely + * on the bootloader for it. + */ pincntl: pinmux@800 { compatible = "pinctrl-single"; - reg = <0x800 0xc38>; + reg = <0x800 0x438>; #address-cells = <1>; #size-cells = <0>; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x300ff>; + pinctrl-single,function-mask = <0x307ff>; }; }; prcm: prcm@180000 { compatible = "ti,dm814-prcm", "simple-bus"; - reg = <0x180000 0x4000>; + reg = <0x180000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x180000 0x2000>; prcm_clocks: clocks { #address-cells = <1>; @@ -226,9 +239,13 @@ }; }; + /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ pllss: pllss@1c5000 { compatible = "ti,dm814-pllss", "simple-bus"; - reg = <0x1c5000 0x2000>; + reg = <0x1c5000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1c5000 0x1000>; pllss_clocks: clocks { #address-cells = <1>; diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 45f4c21e393c..e0df333202b8 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -84,7 +84,7 @@ static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset) struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); /* XXX: I'm unsure, but it seems so */ - return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)); + return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1))); } static int scoop_gpio_direction_input(struct gpio_chip *chip, diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index dd8f5312b2c0..bcaf1d025505 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -34,7 +34,8 @@ config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137/AM17x based system" depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR select ARCH_DAVINCI_DA8XX - select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 + # needed on silicon revs 1.0, 1.1: + select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE select CP_INTC config ARCH_DAVINCI_DA850 diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index c71dd9982f03..1844076f6403 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -384,9 +384,7 @@ static __init void dm355_evm_init(void) dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); - if (IS_ERR(aemif)) - WARN("%s: unable to get AEMIF clock\n", __func__); - else + if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) clk_prepare_enable(aemif); platform_add_devices(davinci_evm_devices, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index 680a7a2d9102..284ff27c1b32 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -242,9 +242,7 @@ static __init void dm355_leopard_init(void) dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); - if (IS_ERR(aemif)) - WARN("%s: unable to get AEMIF clock\n", __func__); - else + if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) clk_prepare_enable(aemif); platform_add_devices(davinci_leopard_devices, diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3eaeaca5da05..3c87e40650cf 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -612,8 +612,7 @@ void __init ti814x_init_early(void) ti814x_clockdomains_init(); dm814x_hwmod_init(); omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) - omap_clk_soc_init = dm814x_dt_clk_init; + omap_clk_soc_init = dm814x_dt_clk_init; } void __init ti816x_init_early(void) diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 6256052893ec..1b96cdfd1558 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -599,7 +599,7 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { static struct omap_hwmod dm814x_timer1_hwmod = { .name = "timer1", .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer_sys_ck", + .main_clk = "timer1_fck", .dev_attr = &capability_alwon_dev_attr, .class = &dm816x_timer_hwmod_class, .flags = HWMOD_NO_IDLEST, @@ -608,7 +608,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = { static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { .master = &dm81xx_l4_ls_hwmod, .slave = &dm814x_timer1_hwmod, - .clk = "timer_sys_ck", + .clk = "timer1_fck", .user = OCP_USER_MPU, }; @@ -636,7 +636,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { static struct omap_hwmod dm814x_timer2_hwmod = { .name = "timer2", .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer_sys_ck", + .main_clk = "timer2_fck", .dev_attr = &capability_alwon_dev_attr, .class = &dm816x_timer_hwmod_class, .flags = HWMOD_NO_IDLEST, @@ -645,7 +645,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = { static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { .master = &dm81xx_l4_ls_hwmod, .slave = &dm814x_timer2_hwmod, - .clk = "timer_sys_ck", + .clk = "timer2_fck", .user = OCP_USER_MPU, }; @@ -1230,8 +1230,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { /* * REVISIT: Test and enable the following once clocks work: - * dm81xx_l4_ls__gpio1 - * dm81xx_l4_ls__gpio2 * dm81xx_l4_ls__mailbox * dm81xx_alwon_l3_slow__gpmc * dm81xx_default_l3_slow__usbss @@ -1250,6 +1248,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm81xx_l4_ls__wd_timer1, &dm81xx_l4_ls__i2c1, &dm81xx_l4_ls__i2c2, + &dm81xx_l4_ls__gpio1, + &dm81xx_l4_ls__gpio2, &dm81xx_l4_ls__elm, &dm81xx_l4_ls__mcspi1, &dm81xx_alwon_l3_fast__tpcc, diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 3fc2cbe52113..5b2f5138d938 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -664,6 +664,13 @@ static struct omap_prcm_init_data am3_prm_data __initdata = { }; #endif +#ifdef CONFIG_SOC_TI81XX +static struct omap_prcm_init_data dm814_pllss_data __initdata = { + .index = TI_CLKM_PLLSS, + .init = am33xx_prm_init, +}; +#endif + #ifdef CONFIG_ARCH_OMAP4 static struct omap_prcm_init_data omap4_prm_data __initdata = { .index = TI_CLKM_PRM, @@ -715,6 +722,7 @@ static const struct of_device_id const omap_prcm_dt_match_table[] __initconst = #endif #ifdef CONFIG_SOC_TI81XX { .compatible = "ti,dm814-prcm", .data = &am3_prm_data }, + { .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data }, { .compatible = "ti,dm816-prcm", .data = &am3_prm_data }, #endif #ifdef CONFIG_ARCH_OMAP2 diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 41e476e571d7..d8965c682d2f 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -98,8 +98,8 @@ static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset) { if (offset > 15) - return simpad_get_cs3_ro() & (1 << (offset - 16)); - return simpad_get_cs3_shadow() & (1 << offset); + return !!(simpad_get_cs3_ro() & (1 << (offset - 16))); + return !!(simpad_get_cs3_shadow() & (1 << offset)); }; static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset) diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c index e172920798ea..9e85fcc74cc9 100644 --- a/drivers/clk/ti/clk-814x.c +++ b/drivers/clk/ti/clk-814x.c @@ -14,10 +14,14 @@ static struct ti_dt_clk dm814_clks[] = { DT_CLK(NULL, "devosc_ck", "devosc_ck"), DT_CLK(NULL, "mpu_ck", "mpu_ck"), DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"), + DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"), DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"), + DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"), DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"), DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"), DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), + DT_CLK(NULL, "timer1_fck", "timer1_fck"), + DT_CLK(NULL, "timer2_fck", "timer2_fck"), DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), { .node_name = NULL }, diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 75205df29b9c..9a638601cb09 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -195,6 +195,7 @@ enum { TI_CLKM_PRM, TI_CLKM_SCRM, TI_CLKM_CTRL, + TI_CLKM_PLLSS, CLK_MAX_MEMMAPS };