drm/vmwgfx: Fix the driver for large dma addresses
With dma compliance / IOMMU support added to the driver in kernel 3.13, the dma addresses can exceed 44 bits, which is what we support in 32-bit mode and with GMR1. So in 32-bit mode and optionally in 64-bit mode, restrict the dma addresses to 44 bits, and strip the old GMR1 code. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Jakob Bornecrantz <jakob@vmware.com> Cc: stable@vger.kernel.org
This commit is contained in:
Thomas Hellstrom
Родитель
c5416d661d
Коммит
0d00c488f3
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@ -189,6 +189,7 @@ static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
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static int vmw_force_iommu;
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static int vmw_restrict_iommu;
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static int vmw_force_coherent;
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static int vmw_restrict_dma_mask;
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static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
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static void vmw_master_init(struct vmw_master *);
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@ -203,6 +204,8 @@ MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
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module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
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MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
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module_param_named(force_coherent, vmw_force_coherent, int, 0600);
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MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
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module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
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static void vmw_print_capabilities(uint32_t capabilities)
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@ -510,6 +513,33 @@ out_fixup:
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return 0;
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}
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/**
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* vmw_dma_masks - set required page- and dma masks
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*
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* @dev: Pointer to struct drm-device
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*
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* With 32-bit we can only handle 32 bit PFNs. Optionally set that
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* restriction also for 64-bit systems.
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*/
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#ifdef CONFIG_INTEL_IOMMU
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static int vmw_dma_masks(struct vmw_private *dev_priv)
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{
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struct drm_device *dev = dev_priv->dev;
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if (intel_iommu_enabled &&
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(sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
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DRM_INFO("Restricting DMA addresses to 44 bits.\n");
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return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
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}
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return 0;
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}
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#else
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static int vmw_dma_masks(struct vmw_private *dev_priv)
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{
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return 0;
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}
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#endif
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static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
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{
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struct vmw_private *dev_priv;
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@ -578,14 +608,9 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
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vmw_get_initial_size(dev_priv);
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if (dev_priv->capabilities & SVGA_CAP_GMR) {
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dev_priv->max_gmr_descriptors =
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vmw_read(dev_priv,
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SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
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if (dev_priv->capabilities & SVGA_CAP_GMR2) {
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dev_priv->max_gmr_ids =
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vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
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}
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if (dev_priv->capabilities & SVGA_CAP_GMR2) {
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dev_priv->max_gmr_pages =
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vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
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dev_priv->memory_size =
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@ -599,17 +624,17 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
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dev_priv->memory_size = 512*1024*1024;
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}
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ret = vmw_dma_masks(dev_priv);
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if (unlikely(ret != 0))
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goto out_err0;
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mutex_unlock(&dev_priv->hw_mutex);
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vmw_print_capabilities(dev_priv->capabilities);
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if (dev_priv->capabilities & SVGA_CAP_GMR) {
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if (dev_priv->capabilities & SVGA_CAP_GMR2) {
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DRM_INFO("Max GMR ids is %u\n",
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(unsigned)dev_priv->max_gmr_ids);
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DRM_INFO("Max GMR descriptors is %u\n",
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(unsigned)dev_priv->max_gmr_descriptors);
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}
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if (dev_priv->capabilities & SVGA_CAP_GMR2) {
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DRM_INFO("Max number of GMR pages is %u\n",
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(unsigned)dev_priv->max_gmr_pages);
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DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
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@ -290,7 +290,6 @@ struct vmw_private {
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__le32 __iomem *mmio_virt;
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int mmio_mtrr;
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uint32_t capabilities;
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uint32_t max_gmr_descriptors;
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uint32_t max_gmr_ids;
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uint32_t max_gmr_pages;
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uint32_t memory_size;
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@ -125,181 +125,27 @@ static void vmw_gmr2_unbind(struct vmw_private *dev_priv,
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}
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static void vmw_gmr_free_descriptors(struct device *dev, dma_addr_t desc_dma,
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struct list_head *desc_pages)
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{
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struct page *page, *next;
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struct svga_guest_mem_descriptor *page_virtual;
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unsigned int desc_per_page = PAGE_SIZE /
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sizeof(struct svga_guest_mem_descriptor) - 1;
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if (list_empty(desc_pages))
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return;
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list_for_each_entry_safe(page, next, desc_pages, lru) {
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list_del_init(&page->lru);
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if (likely(desc_dma != DMA_ADDR_INVALID)) {
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dma_unmap_page(dev, desc_dma, PAGE_SIZE,
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DMA_TO_DEVICE);
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}
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page_virtual = kmap_atomic(page);
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desc_dma = (dma_addr_t)
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le32_to_cpu(page_virtual[desc_per_page].ppn) <<
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PAGE_SHIFT;
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kunmap_atomic(page_virtual);
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__free_page(page);
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}
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}
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/**
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* FIXME: Adjust to the ttm lowmem / highmem storage to minimize
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* the number of used descriptors.
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*
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*/
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static int vmw_gmr_build_descriptors(struct device *dev,
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struct list_head *desc_pages,
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struct vmw_piter *iter,
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unsigned long num_pages,
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dma_addr_t *first_dma)
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{
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struct page *page;
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struct svga_guest_mem_descriptor *page_virtual = NULL;
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struct svga_guest_mem_descriptor *desc_virtual = NULL;
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unsigned int desc_per_page;
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unsigned long prev_pfn;
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unsigned long pfn;
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int ret;
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dma_addr_t desc_dma;
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desc_per_page = PAGE_SIZE /
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sizeof(struct svga_guest_mem_descriptor) - 1;
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while (likely(num_pages != 0)) {
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page = alloc_page(__GFP_HIGHMEM);
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if (unlikely(page == NULL)) {
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ret = -ENOMEM;
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goto out_err;
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}
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list_add_tail(&page->lru, desc_pages);
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page_virtual = kmap_atomic(page);
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desc_virtual = page_virtual - 1;
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prev_pfn = ~(0UL);
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while (likely(num_pages != 0)) {
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pfn = vmw_piter_dma_addr(iter) >> PAGE_SHIFT;
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if (pfn != prev_pfn + 1) {
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if (desc_virtual - page_virtual ==
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desc_per_page - 1)
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break;
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(++desc_virtual)->ppn = cpu_to_le32(pfn);
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desc_virtual->num_pages = cpu_to_le32(1);
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} else {
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uint32_t tmp =
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le32_to_cpu(desc_virtual->num_pages);
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desc_virtual->num_pages = cpu_to_le32(tmp + 1);
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}
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prev_pfn = pfn;
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--num_pages;
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vmw_piter_next(iter);
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}
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(++desc_virtual)->ppn = DMA_PAGE_INVALID;
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desc_virtual->num_pages = cpu_to_le32(0);
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kunmap_atomic(page_virtual);
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}
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desc_dma = 0;
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list_for_each_entry_reverse(page, desc_pages, lru) {
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page_virtual = kmap_atomic(page);
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page_virtual[desc_per_page].ppn = cpu_to_le32
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(desc_dma >> PAGE_SHIFT);
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kunmap_atomic(page_virtual);
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desc_dma = dma_map_page(dev, page, 0, PAGE_SIZE,
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DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(dev, desc_dma)))
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goto out_err;
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}
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*first_dma = desc_dma;
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return 0;
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out_err:
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vmw_gmr_free_descriptors(dev, DMA_ADDR_INVALID, desc_pages);
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return ret;
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}
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static void vmw_gmr_fire_descriptors(struct vmw_private *dev_priv,
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int gmr_id, dma_addr_t desc_dma)
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{
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mutex_lock(&dev_priv->hw_mutex);
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vmw_write(dev_priv, SVGA_REG_GMR_ID, gmr_id);
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wmb();
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vmw_write(dev_priv, SVGA_REG_GMR_DESCRIPTOR, desc_dma >> PAGE_SHIFT);
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mb();
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mutex_unlock(&dev_priv->hw_mutex);
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}
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int vmw_gmr_bind(struct vmw_private *dev_priv,
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const struct vmw_sg_table *vsgt,
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unsigned long num_pages,
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int gmr_id)
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{
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struct list_head desc_pages;
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dma_addr_t desc_dma = 0;
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struct device *dev = dev_priv->dev->dev;
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struct vmw_piter data_iter;
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int ret;
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vmw_piter_start(&data_iter, vsgt, 0);
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if (unlikely(!vmw_piter_next(&data_iter)))
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return 0;
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if (likely(dev_priv->capabilities & SVGA_CAP_GMR2))
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if (unlikely(!(dev_priv->capabilities & SVGA_CAP_GMR2)))
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return -EINVAL;
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return vmw_gmr2_bind(dev_priv, &data_iter, num_pages, gmr_id);
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if (unlikely(!(dev_priv->capabilities & SVGA_CAP_GMR)))
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return -EINVAL;
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if (vsgt->num_regions > dev_priv->max_gmr_descriptors)
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return -EINVAL;
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INIT_LIST_HEAD(&desc_pages);
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ret = vmw_gmr_build_descriptors(dev, &desc_pages, &data_iter,
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num_pages, &desc_dma);
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if (unlikely(ret != 0))
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return ret;
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vmw_gmr_fire_descriptors(dev_priv, gmr_id, desc_dma);
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vmw_gmr_free_descriptors(dev, desc_dma, &desc_pages);
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return 0;
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}
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void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id)
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{
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if (likely(dev_priv->capabilities & SVGA_CAP_GMR2)) {
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if (likely(dev_priv->capabilities & SVGA_CAP_GMR2))
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vmw_gmr2_unbind(dev_priv, gmr_id);
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return;
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}
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mutex_lock(&dev_priv->hw_mutex);
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vmw_write(dev_priv, SVGA_REG_GMR_ID, gmr_id);
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wmb();
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vmw_write(dev_priv, SVGA_REG_GMR_DESCRIPTOR, 0);
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mb();
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mutex_unlock(&dev_priv->hw_mutex);
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}
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