drm/amdgpu: add new atomfirmware based helpers for powerplay
New helpers for fetching info out of atomfirmware. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Ken Wang <Ken.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang
Alex Deucher
Родитель
bcea239686
Коммит
0d2c7569e1
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@ -5,7 +5,7 @@
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HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
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hardwaremanager.o pp_acpi.o cz_hwmgr.o \
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cz_clockpowergating.o pppcielanes.o\
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process_pptables_v1_0.o ppatomctrl.o \
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process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
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smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
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smu7_clockpowergating.o
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@ -0,0 +1,396 @@
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "ppatomfwctrl.h"
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#include "atomfirmware.h"
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#include "pp_debug.h"
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static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4(
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const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table,
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uint8_t voltage_type, uint8_t voltage_mode)
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{
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unsigned int size = le16_to_cpu(
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voltage_object_info_table->table_header.structuresize);
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unsigned int offset =
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offsetof(struct atom_voltage_objects_info_v4_1, voltage_object[0]);
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unsigned long start = (unsigned long)voltage_object_info_table;
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while (offset < size) {
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const union atom_voltage_object_v4 *voltage_object =
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(const union atom_voltage_object_v4 *)(start + offset);
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if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&
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voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)
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return voltage_object;
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offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
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}
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return NULL;
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}
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static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table(
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struct pp_hwmgr *hwmgr)
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{
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const void *table_address;
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uint16_t idx;
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idx = GetIndexIntoMasterDataTable(voltageobject_info);
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table_address = cgs_atom_get_data_table(hwmgr->device,
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idx, NULL, NULL, NULL);
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PP_ASSERT_WITH_CODE(
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table_address,
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"Error retrieving BIOS Table Address!",
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return NULL);
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return (struct atom_voltage_objects_info_v4_1 *)table_address;
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}
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/**
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* Returns TRUE if the given voltage type is controlled by GPIO pins.
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* voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC, SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
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* voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
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*/
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bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
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uint8_t voltage_type, uint8_t voltage_mode)
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{
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struct atom_voltage_objects_info_v4_1 *voltage_info =
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(struct atom_voltage_objects_info_v4_1 *)
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pp_atomfwctrl_get_voltage_info_table(hwmgr);
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bool ret;
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/* If we cannot find the table do NOT try to control this voltage. */
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PP_ASSERT_WITH_CODE(voltage_info,
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"Could not find Voltage Table in BIOS.",
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return false);
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ret = (pp_atomfwctrl_lookup_voltage_type_v4(voltage_info,
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voltage_type, voltage_mode)) ? true : false;
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return ret;
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}
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int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr,
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uint8_t voltage_type, uint8_t voltage_mode,
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struct pp_atomfwctrl_voltage_table *voltage_table)
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{
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struct atom_voltage_objects_info_v4_1 *voltage_info =
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(struct atom_voltage_objects_info_v4_1 *)
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pp_atomfwctrl_get_voltage_info_table(hwmgr);
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const union atom_voltage_object_v4 *voltage_object;
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unsigned int i;
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int result = 0;
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PP_ASSERT_WITH_CODE(voltage_info,
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"Could not find Voltage Table in BIOS.",
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return -1);
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voltage_object = pp_atomfwctrl_lookup_voltage_type_v4(voltage_info,
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voltage_type, voltage_mode);
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if (!voltage_object)
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return -1;
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voltage_table->count = 0;
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if (voltage_mode == VOLTAGE_OBJ_GPIO_LUT) {
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PP_ASSERT_WITH_CODE(
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(voltage_object->gpio_voltage_obj.gpio_entry_num <=
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PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES),
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"Too many voltage entries!",
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result = -1);
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if (!result) {
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for (i = 0; i < voltage_object->gpio_voltage_obj.
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gpio_entry_num; i++) {
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voltage_table->entries[i].value =
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le16_to_cpu(voltage_object->gpio_voltage_obj.
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voltage_gpio_lut[i].voltage_level_mv);
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voltage_table->entries[i].smio_low =
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le32_to_cpu(voltage_object->gpio_voltage_obj.
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voltage_gpio_lut[i].voltage_gpio_reg_val);
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}
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voltage_table->count =
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voltage_object->gpio_voltage_obj.gpio_entry_num;
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voltage_table->mask_low =
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le32_to_cpu(
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voltage_object->gpio_voltage_obj.gpio_mask_val);
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voltage_table->phase_delay =
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voltage_object->gpio_voltage_obj.phase_delay_us;
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}
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} else if (voltage_mode == VOLTAGE_OBJ_SVID2) {
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voltage_table->psi1_enable =
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voltage_object->svid2_voltage_obj.loadline_psi1 & 0x1;
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voltage_table->psi0_enable =
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voltage_object->svid2_voltage_obj.psi0_enable & 0x1;
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voltage_table->max_vid_step =
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voltage_object->svid2_voltage_obj.maxvstep;
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voltage_table->telemetry_offset =
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voltage_object->svid2_voltage_obj.telemetry_offset;
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voltage_table->telemetry_slope =
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voltage_object->svid2_voltage_obj.telemetry_gain;
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} else
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PP_ASSERT_WITH_CODE(false,
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"Unsupported Voltage Object Mode!",
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result = -1);
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return result;
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}
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static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table(
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struct pp_hwmgr *hwmgr)
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{
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const void *table_address;
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uint16_t idx;
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idx = GetIndexIntoMasterDataTable(gpio_pin_lut);
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table_address = cgs_atom_get_data_table(hwmgr->device,
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idx, NULL, NULL, NULL);
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PP_ASSERT_WITH_CODE(table_address,
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"Error retrieving BIOS Table Address!",
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return NULL);
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return (struct atom_gpio_pin_lut_v2_1 *)table_address;
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}
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static bool pp_atomfwctrl_lookup_gpio_pin(
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struct atom_gpio_pin_lut_v2_1 *gpio_lookup_table,
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const uint32_t pin_id,
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struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment)
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{
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unsigned int size = le16_to_cpu(
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gpio_lookup_table->table_header.structuresize);
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unsigned int offset =
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offsetof(struct atom_gpio_pin_lut_v2_1, gpio_pin[0]);
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unsigned long start = (unsigned long)gpio_lookup_table;
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while (offset < size) {
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const struct atom_gpio_pin_assignment *pin_assignment =
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(const struct atom_gpio_pin_assignment *)(start + offset);
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if (pin_id == pin_assignment->gpio_id) {
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gpio_pin_assignment->uc_gpio_pin_bit_shift =
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pin_assignment->gpio_bitshift;
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gpio_pin_assignment->us_gpio_pin_aindex =
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le16_to_cpu(pin_assignment->data_a_reg_index);
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return true;
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}
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offset += offsetof(struct atom_gpio_pin_assignment, gpio_id) + 1;
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}
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return false;
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}
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/**
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* Returns TRUE if the given pin id find in lookup table.
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*/
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bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr,
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const uint32_t pin_id,
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struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment)
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{
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bool ret = false;
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struct atom_gpio_pin_lut_v2_1 *gpio_lookup_table =
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pp_atomfwctrl_get_gpio_lookup_table(hwmgr);
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/* If we cannot find the table do NOT try to control this voltage. */
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PP_ASSERT_WITH_CODE(gpio_lookup_table,
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"Could not find GPIO lookup Table in BIOS.",
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return false);
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ret = pp_atomfwctrl_lookup_gpio_pin(gpio_lookup_table,
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pin_id, gpio_pin_assignment);
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return ret;
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}
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/**
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* Enter to SelfRefresh mode.
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* @param hwmgr
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*/
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int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr)
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{
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/* 0 - no action
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* 1 - leave power to video memory always on
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*/
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return 0;
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}
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/** pp_atomfwctrl_get_gpu_pll_dividers_vega10().
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*
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* @param hwmgr input parameter: pointer to HwMgr
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* @param clock_type input parameter: Clock type: 1 - GFXCLK, 2 - UCLK, 0 - All other clocks
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* @param clock_value input parameter: Clock
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* @param dividers output parameter:Clock dividers
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*/
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int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
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uint32_t clock_type, uint32_t clock_value,
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struct pp_atomfwctrl_clock_dividers_soc15 *dividers)
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{
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struct compute_gpu_clock_input_parameter_v1_8 pll_parameters;
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struct compute_gpu_clock_output_parameter_v1_8 *pll_output;
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int result;
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uint32_t idx;
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pll_parameters.gpuclock_10khz = (uint32_t)clock_value;
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pll_parameters.gpu_clock_type = clock_type;
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idx = GetIndexIntoMasterCmdTable(computegpuclockparam);
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result = cgs_atom_exec_cmd_table(hwmgr->device, idx, &pll_parameters);
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if (!result) {
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pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)
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&pll_parameters;
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dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
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dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
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dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
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dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
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dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
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dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
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}
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return result;
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}
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int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_avfs_parameters *param)
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{
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uint16_t idx;
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struct atom_asic_profiling_info_v4_1 *profile;
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idx = GetIndexIntoMasterDataTable(asic_profiling_info);
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profile = (struct atom_asic_profiling_info_v4_1 *)
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cgs_atom_get_data_table(hwmgr->device,
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idx, NULL, NULL, NULL);
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if (!profile)
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return -1;
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param->ulMaxVddc = le32_to_cpu(profile->maxvddc);
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param->ulMinVddc = le32_to_cpu(profile->minvddc);
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param->ulMeanNsigmaAcontant0 =
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le32_to_cpu(profile->avfs_meannsigma_acontant0);
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param->ulMeanNsigmaAcontant1 =
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le32_to_cpu(profile->avfs_meannsigma_acontant1);
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param->ulMeanNsigmaAcontant2 =
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le32_to_cpu(profile->avfs_meannsigma_acontant2);
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param->usMeanNsigmaDcTolSigma =
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le16_to_cpu(profile->avfs_meannsigma_dc_tol_sigma);
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param->usMeanNsigmaPlatformMean =
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le16_to_cpu(profile->avfs_meannsigma_platform_mean);
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param->usMeanNsigmaPlatformSigma =
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le16_to_cpu(profile->avfs_meannsigma_platform_sigma);
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param->ulGbVdroopTableCksoffA0 =
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le32_to_cpu(profile->gb_vdroop_table_cksoff_a0);
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param->ulGbVdroopTableCksoffA1 =
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le32_to_cpu(profile->gb_vdroop_table_cksoff_a1);
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param->ulGbVdroopTableCksoffA2 =
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le32_to_cpu(profile->gb_vdroop_table_cksoff_a2);
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param->ulGbVdroopTableCksonA0 =
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le32_to_cpu(profile->gb_vdroop_table_ckson_a0);
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param->ulGbVdroopTableCksonA1 =
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le32_to_cpu(profile->gb_vdroop_table_ckson_a1);
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param->ulGbVdroopTableCksonA2 =
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le32_to_cpu(profile->gb_vdroop_table_ckson_a2);
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param->ulGbFuseTableCksoffM1 =
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le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m1);
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param->usGbFuseTableCksoffM2 =
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le16_to_cpu(profile->avfsgb_fuse_table_cksoff_m2);
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param->ulGbFuseTableCksoffB =
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le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b);
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param->ulGbFuseTableCksonM1 =
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le32_to_cpu(profile->avfsgb_fuse_table_ckson_m1);
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param->usGbFuseTableCksonM2 =
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le16_to_cpu(profile->avfsgb_fuse_table_ckson_m2);
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param->ulGbFuseTableCksonB =
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le32_to_cpu(profile->avfsgb_fuse_table_ckson_b);
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param->usMaxVoltage025mv =
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le16_to_cpu(profile->max_voltage_0_25mv);
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param->ucEnableGbVdroopTableCksoff =
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profile->enable_gb_vdroop_table_cksoff;
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param->ucEnableGbVdroopTableCkson =
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profile->enable_gb_vdroop_table_ckson;
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param->ucEnableGbFuseTableCksoff =
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profile->enable_gb_fuse_table_cksoff;
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param->ucEnableGbFuseTableCkson =
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profile->enable_gb_fuse_table_ckson;
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param->usPsmAgeComfactor =
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le16_to_cpu(profile->psm_age_comfactor);
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param->ucEnableApplyAvfsCksoffVoltage =
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profile->enable_apply_avfs_cksoff_voltage;
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param->ulDispclk2GfxclkM1 =
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le32_to_cpu(profile->dispclk2gfxclk_a);
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param->usDispclk2GfxclkM2 =
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le16_to_cpu(profile->dispclk2gfxclk_b);
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param->ulDispclk2GfxclkB =
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le32_to_cpu(profile->dispclk2gfxclk_c);
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param->ulDcefclk2GfxclkM1 =
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le32_to_cpu(profile->dcefclk2gfxclk_a);
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param->usDcefclk2GfxclkM2 =
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le16_to_cpu(profile->dcefclk2gfxclk_b);
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param->ulDcefclk2GfxclkB =
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le32_to_cpu(profile->dcefclk2gfxclk_c);
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param->ulPixelclk2GfxclkM1 =
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le32_to_cpu(profile->pixclk2gfxclk_a);
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param->usPixelclk2GfxclkM2 =
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le16_to_cpu(profile->pixclk2gfxclk_b);
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param->ulPixelclk2GfxclkB =
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le32_to_cpu(profile->pixclk2gfxclk_c);
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param->ulPhyclk2GfxclkM1 =
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le32_to_cpu(profile->phyclk2gfxclk_a);
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param->usPhyclk2GfxclkM2 =
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le16_to_cpu(profile->phyclk2gfxclk_b);
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param->ulPhyclk2GfxclkB =
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le32_to_cpu(profile->phyclk2gfxclk_c);
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return 0;
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}
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int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_gpio_parameters *param)
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{
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struct atom_smu_info_v3_1 *info;
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uint16_t idx;
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||||
idx = GetIndexIntoMasterDataTable(smu_info);
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info = (struct atom_smu_info_v3_1 *)
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cgs_atom_get_data_table(hwmgr->device,
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idx, NULL, NULL, NULL);
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if (!info) {
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pr_info("Error retrieving BIOS smu_info Table Address!");
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return -1;
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}
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||||
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param->ucAcDcGpio = info->ac_dc_gpio_bit;
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param->ucAcDcPolarity = info->ac_dc_polarity;
|
||||
param->ucVR0HotGpio = info->vr0hot_gpio_bit;
|
||||
param->ucVR0HotPolarity = info->vr0hot_polarity;
|
||||
param->ucVR1HotGpio = info->vr1hot_gpio_bit;
|
||||
param->ucVR1HotPolarity = info->vr1hot_polarity;
|
||||
param->ucFwCtfGpio = info->fw_ctf_gpio_bit;
|
||||
param->ucFwCtfPolarity = info->fw_ctf_polarity;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PP_ATOMFWCTRL_H
|
||||
#define PP_ATOMFWCTRL_H
|
||||
|
||||
#include "hwmgr.h"
|
||||
|
||||
#define GetIndexIntoMasterCmdTable(FieldName) \
|
||||
(((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
|
||||
#define GetIndexIntoMasterDataTable(FieldName) \
|
||||
(((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
|
||||
|
||||
#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
|
||||
|
||||
struct pp_atomfwctrl_voltage_table_entry {
|
||||
uint16_t value;
|
||||
uint32_t smio_low;
|
||||
};
|
||||
|
||||
struct pp_atomfwctrl_voltage_table {
|
||||
uint32_t count;
|
||||
uint32_t mask_low;
|
||||
uint32_t phase_delay;
|
||||
uint8_t psi0_enable;
|
||||
uint8_t psi1_enable;
|
||||
uint8_t max_vid_step;
|
||||
uint8_t telemetry_offset;
|
||||
uint8_t telemetry_slope;
|
||||
struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
|
||||
};
|
||||
|
||||
struct pp_atomfwctrl_gpio_pin_assignment {
|
||||
uint16_t us_gpio_pin_aindex;
|
||||
uint8_t uc_gpio_pin_bit_shift;
|
||||
};
|
||||
|
||||
struct pp_atomfwctrl_clock_dividers_soc15 {
|
||||
uint32_t ulClock; /* the actual clock */
|
||||
uint32_t ulDid; /* DFS divider */
|
||||
uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
|
||||
uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
|
||||
uint16_t usPll_ss_slew_frac;
|
||||
uint8_t ucPll_ss_enable;
|
||||
uint8_t ucReserve;
|
||||
uint32_t ulReserve[2];
|
||||
};
|
||||
|
||||
struct pp_atomfwctrl_avfs_parameters {
|
||||
uint32_t ulMaxVddc;
|
||||
uint32_t ulMinVddc;
|
||||
uint8_t ucMaxVidStep;
|
||||
uint32_t ulMeanNsigmaAcontant0;
|
||||
uint32_t ulMeanNsigmaAcontant1;
|
||||
uint32_t ulMeanNsigmaAcontant2;
|
||||
uint16_t usMeanNsigmaDcTolSigma;
|
||||
uint16_t usMeanNsigmaPlatformMean;
|
||||
uint16_t usMeanNsigmaPlatformSigma;
|
||||
uint32_t ulGbVdroopTableCksoffA0;
|
||||
uint32_t ulGbVdroopTableCksoffA1;
|
||||
uint32_t ulGbVdroopTableCksoffA2;
|
||||
uint32_t ulGbVdroopTableCksonA0;
|
||||
uint32_t ulGbVdroopTableCksonA1;
|
||||
uint32_t ulGbVdroopTableCksonA2;
|
||||
uint32_t ulGbFuseTableCksoffM1;
|
||||
uint16_t usGbFuseTableCksoffM2;
|
||||
uint32_t ulGbFuseTableCksoffB;\
|
||||
uint32_t ulGbFuseTableCksonM1;
|
||||
uint16_t usGbFuseTableCksonM2;
|
||||
uint32_t ulGbFuseTableCksonB;
|
||||
uint16_t usMaxVoltage025mv;
|
||||
uint8_t ucEnableGbVdroopTableCksoff;
|
||||
uint8_t ucEnableGbVdroopTableCkson;
|
||||
uint8_t ucEnableGbFuseTableCksoff;
|
||||
uint8_t ucEnableGbFuseTableCkson;
|
||||
uint16_t usPsmAgeComfactor;
|
||||
uint8_t ucEnableApplyAvfsCksoffVoltage;
|
||||
uint32_t ulDispclk2GfxclkM1;
|
||||
uint16_t usDispclk2GfxclkM2;
|
||||
uint32_t ulDispclk2GfxclkB;
|
||||
uint32_t ulDcefclk2GfxclkM1;
|
||||
uint16_t usDcefclk2GfxclkM2;
|
||||
uint32_t ulDcefclk2GfxclkB;
|
||||
uint32_t ulPixelclk2GfxclkM1;
|
||||
uint16_t usPixelclk2GfxclkM2;
|
||||
uint32_t ulPixelclk2GfxclkB;
|
||||
uint32_t ulPhyclk2GfxclkM1;
|
||||
uint16_t usPhyclk2GfxclkM2;
|
||||
uint32_t ulPhyclk2GfxclkB;
|
||||
};
|
||||
|
||||
struct pp_atomfwctrl_gpio_parameters {
|
||||
uint8_t ucAcDcGpio;
|
||||
uint8_t ucAcDcPolarity;
|
||||
uint8_t ucVR0HotGpio;
|
||||
uint8_t ucVR0HotPolarity;
|
||||
uint8_t ucVR1HotGpio;
|
||||
uint8_t ucVR1HotPolarity;
|
||||
uint8_t ucFwCtfGpio;
|
||||
uint8_t ucFwCtfPolarity;
|
||||
};
|
||||
int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
|
||||
uint32_t clock_type, uint32_t clock_value,
|
||||
struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
|
||||
int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
|
||||
bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
|
||||
struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
|
||||
|
||||
int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
||||
uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
|
||||
bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
|
||||
uint8_t voltage_type, uint8_t voltage_mode);
|
||||
|
||||
int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
|
||||
struct pp_atomfwctrl_avfs_parameters *param);
|
||||
int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
|
||||
struct pp_atomfwctrl_gpio_parameters *param);
|
||||
|
||||
#endif
|
||||
|
||||
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