IXP4xx: use __iomem for MMIO
The ixp4xx queue manager uses "const struct qmgr_regs __iomem *" as the type for a pointer that is passed to __raw_writel, which is not allowed because of the const-ness. Dropping the 'const' keyword fixes the problem. While we're here, let's also drop the useless type cast. Without this patch, building ixp4xx_defconfig results in: In file included from arch/arm/mach-ixp4xx/ixp4xx_qmgr.c:15:0: arch/arm/mach-ixp4xx/include/mach/qmgr.h: In function 'qmgr_put_entry': arch/arm/mach-ixp4xx/include/mach/qmgr.h:96:2: warning: passing argument 2 of '__raw_writel' discards 'const' qualifier from pointer target type [enabled by default] arch/arm/include/asm/io.h:88:91: note: expected 'volatile void *' but argument is of type 'const u32 *' In file included from drivers/net/ethernet/xscale/ixp4xx_eth.c:41:0: arch/arm/mach-ixp4xx/include/mach/qmgr.h: In function 'qmgr_put_entry': arch/arm/mach-ixp4xx/include/mach/qmgr.h:96:2: warning: passing argument 2 of '__raw_writel' discards 'const' qualifier from pointer target type [enabled by default] arch/arm/include/asm/io.h:88:91: note: expected 'volatile void *' but argument is of type 'const u32 *' arch/arm/mach-ixp4xx/ixp4xx_qmgr.c: In function 'qmgr_set_irq': arch/arm/mach-ixp4xx/ixp4xx_qmgr.c:41:9: warning: passing argument 2 of '__raw_writel' discards 'const' qualifier from pointer target type [enabled by default] arch/arm/include/asm/io.h:88:91: note: expected 'volatile void *' but argument is of type 'const u32 *' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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0d2c9f0517
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@ -86,7 +86,7 @@ void qmgr_release_queue(unsigned int queue);
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static inline void qmgr_put_entry(unsigned int queue, u32 val)
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{
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
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#if DEBUG_QMGR
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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@ -99,7 +99,7 @@ static inline void qmgr_put_entry(unsigned int queue, u32 val)
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static inline u32 qmgr_get_entry(unsigned int queue)
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{
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u32 val;
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
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val = __raw_readl(&qmgr_regs->acc[queue][0]);
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#if DEBUG_QMGR
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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@ -112,14 +112,14 @@ static inline u32 qmgr_get_entry(unsigned int queue)
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static inline int __qmgr_get_stat1(unsigned int queue)
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{
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
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return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
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>> ((queue & 7) << 2)) & 0xF;
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}
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static inline int __qmgr_get_stat2(unsigned int queue)
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{
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
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BUG_ON(queue >= HALF_QUEUES);
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return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
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>> ((queue & 0xF) << 1)) & 0x3;
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@ -145,7 +145,7 @@ static inline int qmgr_stat_empty(unsigned int queue)
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*/
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static inline int qmgr_stat_below_low_watermark(unsigned int queue)
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{
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
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if (queue >= HALF_QUEUES)
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return (__raw_readl(&qmgr_regs->statne_h) >>
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(queue - HALF_QUEUES)) & 0x01;
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@ -172,7 +172,7 @@ static inline int qmgr_stat_above_high_watermark(unsigned int queue)
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*/
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static inline int qmgr_stat_full(unsigned int queue)
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{
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
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if (queue >= HALF_QUEUES)
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return (__raw_readl(&qmgr_regs->statf_h) >>
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(queue - HALF_QUEUES)) & 0x01;
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@ -14,7 +14,7 @@
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#include <linux/module.h>
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#include <mach/qmgr.h>
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static const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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static struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
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static struct resource *mem_res;
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static spinlock_t qmgr_lock;
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static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
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@ -32,7 +32,7 @@ void qmgr_set_irq(unsigned int queue, int src,
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spin_lock_irqsave(&qmgr_lock, flags);
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if (queue < HALF_QUEUES) {
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const u32 __iomem *reg;
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u32 __iomem *reg;
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int bit;
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BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
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reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
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