Merge branch 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux into late/kirkwood
* 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: add address decoding controller to the DT arm: mvebu: add basic address decoding support to Armada 370/XP arm: plat-orion: make bridge_virt_base non-const to support DT use case arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option arm: plat-orion: use void __iomem pointers for addr-map functions arm: plat-orion: use void __iomem pointers for time functions arm: plat-orion: use void __iomem pointers for MPP functions arm: plat-orion: use void __iomem pointers for UART registration functions arm: mach-mvebu: use IOMEM() for base address definitions arm: mach-orion5x: use IOMEM() for base address definitions arm: mach-mv78xx0: use IOMEM() for base address definitions arm: mach-kirkwood: use IOMEM() for base address definitions arm: mach-dove: use IOMEM() for base address definitions arm: mach-orion5x: use plus instead of or for address definitions arm: mach-mv78xx0: use plus instead of or for address definitions arm: mach-kirkwood: use plus instead of or for address definitions arm: mach-dove: use plus instead of or for address definitions This branch had quite a few conflicts, in particular with the PCI static map rework from Rob Herring, and a few other context conflicts due to changes in Kconfig, etc. I fixed up conflicts in: arch/arm/Kconfig arch/arm/mach-dove/common.c arch/arm/mach-dove/include/mach/dove.h arch/arm/mach-kirkwood/common.c arch/arm/mach-kirkwood/include/mach/kirkwood.h arch/arm/mach-mv78xx0/common.c arch/arm/mach-mv78xx0/include/mach/mv78xx0.h arch/arm/mach-orion5x/common.c arch/arm/mach-orion5x/include/mach/orion5x.h Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
0d601f613b
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@ -540,7 +540,7 @@ config ARCH_DOVE
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select MIGHT_HAVE_PCI
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select PLAT_ORION
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select PLAT_ORION_LEGACY
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select USB_ARCH_HAS_EHCI
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help
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Support for the Marvell Dove SoC 88AP510
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@ -551,7 +551,7 @@ config ARCH_KIRKWOOD
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select PCI
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select PLAT_ORION
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select PLAT_ORION_LEGACY
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help
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Support for the following Marvell Kirkwood series SoCs:
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88F6180, 88F6192 and 88F6281.
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@ -577,7 +577,7 @@ config ARCH_MV78XX0
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select PCI
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select PLAT_ORION
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select PLAT_ORION_LEGACY
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help
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Support for the following Marvell MV78xx0 series SoCs:
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MV781x0, MV782x0.
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@ -589,7 +589,7 @@ config ARCH_ORION5X
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select PCI
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select PLAT_ORION
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select PLAT_ORION_LEGACY
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help
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Support for the following Marvell Orion 5x series SoCs:
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Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
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@ -1146,6 +1146,10 @@ config PLAT_ORION
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select IRQ_DOMAIN
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select COMMON_CLK
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config PLAT_ORION_LEGACY
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bool
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select PLAT_ORION
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config PLAT_PXA
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bool
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@ -63,6 +63,11 @@
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reg = <0xd0020300 0x30>;
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interrupts = <37>, <38>, <39>, <40>;
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};
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addr-decoding@d0020000 {
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compatible = "marvell,armada-addr-decoding-controller";
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reg = <0xd0020000 0x258>;
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};
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};
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};
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@ -41,12 +41,12 @@
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****************************************************************************/
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static struct map_desc dove_io_desc[] __initdata = {
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{
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.virtual = DOVE_SB_REGS_VIRT_BASE,
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.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
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.length = DOVE_SB_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = DOVE_NB_REGS_VIRT_BASE,
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.virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
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.length = DOVE_NB_REGS_SIZE,
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.type = MT_DEVICE,
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@ -13,22 +13,22 @@
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#include <mach/dove.h>
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#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)
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#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
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#define CPU_CTRL_PCIE0_LINK 0x00000001
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#define CPU_RESET 0x00000002
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#define CPU_CTRL_PCIE1_LINK 0x00000008
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define FIQ_MASK_LOW_OFF 0x0008
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@ -47,9 +47,9 @@
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#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
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#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
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#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
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#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
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#endif
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@ -25,7 +25,7 @@
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*/
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#define DOVE_CESA_PHYS_BASE 0xc8000000
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#define DOVE_CESA_VIRT_BASE 0xfdb00000
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#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
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#define DOVE_CESA_SIZE SZ_1M
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#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
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@ -38,15 +38,15 @@
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#define DOVE_BOOTROM_SIZE SZ_128M
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#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
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#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000
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#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
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#define DOVE_SCRATCHPAD_SIZE SZ_1M
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#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
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#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
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#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
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#define DOVE_SB_REGS_SIZE SZ_8M
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#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
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#define DOVE_NB_REGS_VIRT_BASE 0xfe600000
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#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
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#define DOVE_NB_REGS_SIZE SZ_8M
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#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
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@ -62,75 +62,75 @@
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*/
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/* SPI, I2C, UART */
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#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000)
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#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000)
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#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000)
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#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100)
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#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100)
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#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200)
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#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200)
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#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300)
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#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300)
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#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600)
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#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600)
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#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
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#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
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#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
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#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
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#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
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#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
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#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
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#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
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#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
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#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
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#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
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/* North-South Bridge */
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#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000)
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#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x20000)
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#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
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#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
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/* Cryptographic Engine */
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#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000)
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#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
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/* PCIe 0 */
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#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000)
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#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
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/* USB */
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#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000)
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#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000)
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#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
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#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
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/* XOR 0 Engine */
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#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800)
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#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800)
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#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
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#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
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#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
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#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
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#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
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#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
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/* XOR 1 Engine */
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#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900)
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#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900)
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#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
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#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
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#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
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#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
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#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
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#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
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/* Gigabit Ethernet */
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#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000)
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#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
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/* PCIe 1 */
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#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000)
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#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
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/* CAFE */
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#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000)
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#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000)
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#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000)
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#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
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#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
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#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
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#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
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#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
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/* SATA */
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#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
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#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
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/* I2S/SPDIF */
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#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
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#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
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#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
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#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
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/* NAND Flash Controller */
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#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
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#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
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/* MPP, GPIO, Reset Sampling */
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#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
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#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
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#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
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#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
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#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
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#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
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#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
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#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
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#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
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#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
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#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
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#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
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#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
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#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
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#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
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#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
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#define DOVE_NAND_GPIO_EN (1 << 0)
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#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
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@ -142,44 +142,44 @@
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#define DOVE_SD0_GPIO_SEL (1 << 0)
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/* Power Management */
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#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
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#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
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#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
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/* Real Time Clock */
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#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
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#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
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/* AC97 */
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#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
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#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
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#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
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#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
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/* Peripheral DMA */
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#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
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#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
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#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
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#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
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#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
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#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
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#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
|
||||
#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
|
||||
#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
|
||||
#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
|
||||
#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
|
||||
#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
|
||||
#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000)
|
||||
#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
|
||||
#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
|
||||
#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
|
||||
#define DOVE_SSP_ON_AU1 (1 << 0)
|
||||
#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
|
||||
#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
|
||||
/* Memory Controller */
|
||||
#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000)
|
||||
#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
|
||||
|
||||
/* LCD Controller */
|
||||
#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
|
||||
#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000)
|
||||
#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
|
||||
#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
|
||||
#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
|
||||
#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
|
||||
#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
|
||||
#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
|
||||
|
||||
/* Graphic Engine */
|
||||
#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000)
|
||||
#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
|
||||
|
||||
/* Video Engine */
|
||||
#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000)
|
||||
#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -100,19 +100,19 @@ void __init dove_init_irq(void)
|
|||
{
|
||||
int i;
|
||||
|
||||
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
|
||||
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
|
||||
orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
|
||||
orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
|
||||
|
||||
/*
|
||||
* Initialize gpiolib for GPIOs 0-71.
|
||||
*/
|
||||
orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
|
||||
orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
|
||||
IRQ_DOVE_GPIO_START, gpio0_irqs);
|
||||
|
||||
orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
|
||||
orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
|
||||
IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
|
||||
|
||||
orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
|
||||
orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
|
||||
IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -182,18 +182,18 @@ static struct hw_pci dove_pci __initdata = {
|
|||
.map_irq = dove_pcie_map_irq,
|
||||
};
|
||||
|
||||
static void __init add_pcie_port(int index, unsigned long base)
|
||||
static void __init add_pcie_port(int index, void __iomem *base)
|
||||
{
|
||||
printk(KERN_INFO "Dove PCIe port %d: ", index);
|
||||
|
||||
if (orion_pcie_link_up((void __iomem *)base)) {
|
||||
if (orion_pcie_link_up(base)) {
|
||||
struct pcie_port *pp = &pcie_port[num_pcie_ports++];
|
||||
|
||||
printk(KERN_INFO "link up\n");
|
||||
|
||||
pp->index = index;
|
||||
pp->root_bus_nr = -1;
|
||||
pp->base = (void __iomem *)base;
|
||||
pp->base = base;
|
||||
spin_lock_init(&pp->conf_lock);
|
||||
memset(&pp->res, 0, sizeof(pp->res));
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
|
|||
/*
|
||||
* Setup MBUS dram target info.
|
||||
*/
|
||||
orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
|
||||
orion_setup_cpu_mbus_target(&addr_map_cfg,
|
||||
(void __iomem *) DDR_WINDOW_CPU_BASE);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
****************************************************************************/
|
||||
static struct map_desc kirkwood_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = KIRKWOOD_REGS_VIRT_BASE,
|
||||
.virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
|
||||
.length = KIRKWOOD_REGS_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
|
|
@ -205,8 +205,7 @@ static struct clk *tclk;
|
|||
|
||||
static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
|
||||
{
|
||||
return clk_register_gate(NULL, name, "tclk", 0,
|
||||
(void __iomem *)CLOCK_GATING_CTRL,
|
||||
return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
|
||||
bit_idx, 0, &gating_lock);
|
||||
}
|
||||
|
||||
|
|
@ -215,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
|
|||
void (*fn_en)(void),
|
||||
void (*fn_dis)(void))
|
||||
{
|
||||
return clk_register_gate_fn(NULL, name, "tclk", 0,
|
||||
(void __iomem *)CLOCK_GATING_CTRL,
|
||||
return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
|
||||
bit_idx, 0, &gating_lock, fn_en, fn_dis);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -13,37 +13,37 @@
|
|||
|
||||
#include <mach/kirkwood.h>
|
||||
|
||||
#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100)
|
||||
#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
|
||||
#define CPU_CONFIG_ERROR_PROP 0x00000004
|
||||
|
||||
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
|
||||
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
|
||||
#define CPU_RESET 0x00000002
|
||||
|
||||
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
|
||||
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
|
||||
#define WDT_RESET_OUT_EN 0x00000002
|
||||
#define SOFT_RESET_OUT_EN 0x00000004
|
||||
|
||||
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
|
||||
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
|
||||
#define SOFT_RESET 0x00000001
|
||||
|
||||
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
|
||||
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
|
||||
#define WDT_INT_REQ 0x0008
|
||||
|
||||
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
||||
|
||||
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
|
||||
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
|
||||
#define IRQ_CAUSE_LOW_OFF 0x0000
|
||||
#define IRQ_MASK_LOW_OFF 0x0004
|
||||
#define IRQ_CAUSE_HIGH_OFF 0x0010
|
||||
#define IRQ_MASK_HIGH_OFF 0x0014
|
||||
|
||||
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
|
||||
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
|
||||
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
|
||||
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
|
||||
|
||||
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
|
||||
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
|
||||
#define L2_WRITETHROUGH 0x00000010
|
||||
|
||||
#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
|
||||
#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
|
||||
#define CGC_BIT_GE0 (0)
|
||||
#define CGC_BIT_PEX0 (2)
|
||||
#define CGC_BIT_USB0 (3)
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
|
||||
|
||||
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
|
||||
#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
|
||||
#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000)
|
||||
#define KIRKWOOD_REGS_SIZE SZ_1M
|
||||
|
||||
#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
|
||||
|
|
@ -59,61 +59,61 @@
|
|||
/*
|
||||
* Register Map
|
||||
*/
|
||||
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
|
||||
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
|
||||
#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418)
|
||||
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
|
||||
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500)
|
||||
#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418)
|
||||
|
||||
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
|
||||
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
|
||||
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
|
||||
#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
|
||||
#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
|
||||
#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140)
|
||||
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
|
||||
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
|
||||
#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
|
||||
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
|
||||
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
|
||||
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
|
||||
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030)
|
||||
#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034)
|
||||
#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
|
||||
#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140)
|
||||
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300)
|
||||
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600)
|
||||
#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
|
||||
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
|
||||
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
|
||||
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
|
||||
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
|
||||
|
||||
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
|
||||
#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
|
||||
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
|
||||
#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
|
||||
|
||||
#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
|
||||
#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
|
||||
|
||||
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
|
||||
#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
|
||||
#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
|
||||
#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
|
||||
#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
|
||||
#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
|
||||
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
|
||||
#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70)
|
||||
#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04)
|
||||
#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
|
||||
#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70)
|
||||
#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04)
|
||||
|
||||
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
|
||||
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
|
||||
|
||||
#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
|
||||
#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
|
||||
#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
|
||||
#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
|
||||
#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
|
||||
#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
|
||||
#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
|
||||
#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
|
||||
#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
|
||||
#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
|
||||
#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
|
||||
#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
|
||||
#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
|
||||
#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
|
||||
#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
|
||||
#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
|
||||
|
||||
#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
|
||||
#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
|
||||
#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
|
||||
#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
|
||||
|
||||
#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
|
||||
#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
|
||||
#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050)
|
||||
#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330)
|
||||
#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050)
|
||||
#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330)
|
||||
#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
|
||||
#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
|
||||
#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050)
|
||||
#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330)
|
||||
#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050)
|
||||
#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330)
|
||||
|
||||
#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
|
||||
#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
|
||||
|
||||
#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
|
||||
#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
|
||||
#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
|
||||
#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
|
||||
|
||||
/*
|
||||
* Supported devices and revisions.
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include <plat/orion-gpio.h>
|
||||
#include <plat/irq.h>
|
||||
|
|
@ -30,14 +31,14 @@ static int __initdata gpio1_irqs[4] = {
|
|||
|
||||
void __init kirkwood_init_irq(void)
|
||||
{
|
||||
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
|
||||
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
|
||||
orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
|
||||
orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
|
||||
|
||||
/*
|
||||
* Initialize gpiolib for GPIOs 0-49.
|
||||
*/
|
||||
orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
|
||||
orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
|
||||
IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
|
||||
orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
|
||||
orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
|
||||
IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
|
|||
void kirkwood_pcie_id(u32 *dev, u32 *rev)
|
||||
{
|
||||
kirkwood_enable_pcie();
|
||||
*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
|
||||
*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
|
||||
*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
|
||||
*rev = orion_pcie_rev(PCIE_VIRT_BASE);
|
||||
}
|
||||
|
||||
struct pcie_port {
|
||||
|
|
@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = {
|
|||
|
||||
static void __init pcie0_ioresources_init(struct pcie_port *pp)
|
||||
{
|
||||
pp->base = (void __iomem *)PCIE_VIRT_BASE;
|
||||
pp->base = PCIE_VIRT_BASE;
|
||||
pp->irq = IRQ_KIRKWOOD_PCIE;
|
||||
|
||||
/*
|
||||
|
|
@ -147,7 +147,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
|
|||
|
||||
static void __init pcie1_ioresources_init(struct pcie_port *pp)
|
||||
{
|
||||
pp->base = (void __iomem *)PCIE1_VIRT_BASE;
|
||||
pp->base = PCIE1_VIRT_BASE;
|
||||
pp->irq = IRQ_KIRKWOOD_PCIE1;
|
||||
|
||||
/*
|
||||
|
|
@ -255,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = {
|
|||
.map_irq = kirkwood_pcie_map_irq,
|
||||
};
|
||||
|
||||
static void __init add_pcie_port(int index, unsigned long base)
|
||||
static void __init add_pcie_port(int index, void __iomem *base)
|
||||
{
|
||||
printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
|
||||
|
||||
if (orion_pcie_link_up((void __iomem *)base)) {
|
||||
if (orion_pcie_link_up(base)) {
|
||||
printk(KERN_INFO "link up\n");
|
||||
pcie_port_map[num_pcie_ports++] = index;
|
||||
} else
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/kirkwood.h>
|
||||
|
|
@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
|
|||
* (Marvell 88sx7042/sata_mv) is known to stop working
|
||||
* after a few minutes.
|
||||
*/
|
||||
orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
|
||||
orion_pcie_reset(PCIE_VIRT_BASE);
|
||||
|
||||
kirkwood_pcie_id(&dev, &rev);
|
||||
if (dev == MV88F6282_DEV_ID)
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
|
|||
* so we don't need to take that into account here.
|
||||
*/
|
||||
|
||||
return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
|
||||
return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -72,10 +72,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
|
|||
*/
|
||||
if (mv78xx0_core_index() == 0)
|
||||
orion_setup_cpu_mbus_target(&addr_map_cfg,
|
||||
DDR_WINDOW_CPU0_BASE);
|
||||
(void __iomem *) DDR_WINDOW_CPU0_BASE);
|
||||
else
|
||||
orion_setup_cpu_mbus_target(&addr_map_cfg,
|
||||
DDR_WINDOW_CPU1_BASE);
|
||||
(void __iomem *) DDR_WINDOW_CPU1_BASE);
|
||||
}
|
||||
|
||||
void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
|
||||
|
|
|
|||
|
|
@ -130,12 +130,12 @@ static int get_tclk(void)
|
|||
****************************************************************************/
|
||||
static struct map_desc mv78xx0_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = MV78XX0_CORE_REGS_VIRT_BASE,
|
||||
.virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
|
||||
.pfn = 0,
|
||||
.length = MV78XX0_CORE_REGS_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = MV78XX0_REGS_VIRT_BASE,
|
||||
.virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
|
||||
.length = MV78XX0_REGS_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
|
|
|
|||
|
|
@ -11,18 +11,18 @@
|
|||
|
||||
#include <mach/mv78xx0.h>
|
||||
|
||||
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
|
||||
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
|
||||
#define L2_WRITETHROUGH 0x00020000
|
||||
|
||||
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
|
||||
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
|
||||
#define SOFT_RESET_OUT_EN 0x00000004
|
||||
|
||||
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
|
||||
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
|
||||
#define SOFT_RESET 0x00000001
|
||||
|
||||
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
||||
|
||||
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
|
||||
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
|
||||
#define IRQ_CAUSE_ERR_OFF 0x0000
|
||||
#define IRQ_CAUSE_LOW_OFF 0x0004
|
||||
#define IRQ_CAUSE_HIGH_OFF 0x0008
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
#define IRQ_MASK_LOW_OFF 0x0010
|
||||
#define IRQ_MASK_HIGH_OFF 0x0014
|
||||
|
||||
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
|
||||
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
|
||||
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
|
||||
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
*/
|
||||
#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
|
||||
#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
|
||||
#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
|
||||
#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
|
||||
#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
|
||||
#define MV78XX0_CORE_REGS_SIZE SZ_16K
|
||||
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
#define MV78XX0_PCIE_IO_SIZE SZ_1M
|
||||
|
||||
#define MV78XX0_REGS_PHYS_BASE 0xf1000000
|
||||
#define MV78XX0_REGS_VIRT_BASE 0xfd000000
|
||||
#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000)
|
||||
#define MV78XX0_REGS_SIZE SZ_1M
|
||||
|
||||
#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
|
||||
|
|
@ -64,47 +64,47 @@
|
|||
/*
|
||||
* Register Map
|
||||
*/
|
||||
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
|
||||
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
|
||||
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570)
|
||||
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
|
||||
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500)
|
||||
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570)
|
||||
|
||||
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
|
||||
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
|
||||
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
|
||||
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
|
||||
#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100)
|
||||
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
|
||||
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100)
|
||||
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
|
||||
#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200)
|
||||
#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200)
|
||||
#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300)
|
||||
#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300)
|
||||
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
|
||||
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
|
||||
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
|
||||
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
|
||||
#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
|
||||
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
|
||||
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
|
||||
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
|
||||
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
|
||||
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
|
||||
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
|
||||
#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
|
||||
#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
|
||||
#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
|
||||
#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
|
||||
|
||||
#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000)
|
||||
#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000)
|
||||
#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
|
||||
#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
|
||||
|
||||
#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000)
|
||||
#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000)
|
||||
#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000)
|
||||
#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000)
|
||||
#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
|
||||
#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
|
||||
#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
|
||||
#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
|
||||
|
||||
#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000)
|
||||
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
|
||||
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
|
||||
#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
|
||||
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
|
||||
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
|
||||
|
||||
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
|
||||
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
|
||||
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
|
||||
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
|
||||
|
||||
#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000)
|
||||
#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000)
|
||||
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
|
||||
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
|
||||
#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
|
||||
#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
|
||||
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
|
||||
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
|
||||
|
||||
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
|
||||
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
|
||||
|
||||
/*
|
||||
* Supported devices and revisions.
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include <plat/orion-gpio.h>
|
||||
#include <plat/irq.h>
|
||||
|
|
@ -24,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
|
|||
|
||||
void __init mv78xx0_init_irq(void)
|
||||
{
|
||||
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
|
||||
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
|
||||
orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
|
||||
orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
|
||||
orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
|
||||
orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
|
||||
|
||||
/*
|
||||
* Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
|
||||
* registers for core #1 are at an offset of 0x18 from those of
|
||||
* core #0.)
|
||||
*/
|
||||
orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
|
||||
orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
|
||||
mv78xx0_core_index() ? 0x18 : 0,
|
||||
IRQ_MV78XX0_GPIO_START, gpio0_irqs);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,8 +34,8 @@ static struct resource pcie_io_space;
|
|||
|
||||
void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
|
||||
{
|
||||
*dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
|
||||
*rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
|
||||
*dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
|
||||
*rev = orion_pcie_rev(PCIE00_VIRT_BASE);
|
||||
}
|
||||
|
||||
u32 pcie_port_size[8] = {
|
||||
|
|
@ -223,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
|
|||
.map_irq = mv78xx0_pcie_map_irq,
|
||||
};
|
||||
|
||||
static void __init add_pcie_port(int maj, int min, unsigned long base)
|
||||
static void __init add_pcie_port(int maj, int min, void __iomem *base)
|
||||
{
|
||||
printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
|
||||
|
||||
if (orion_pcie_link_up((void __iomem *)base)) {
|
||||
if (orion_pcie_link_up(base)) {
|
||||
struct pcie_port *pp = &pcie_port[num_pcie_ports++];
|
||||
|
||||
printk("link up\n");
|
||||
|
|
@ -235,7 +235,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
|
|||
pp->maj = maj;
|
||||
pp->min = min;
|
||||
pp->root_bus_nr = -1;
|
||||
pp->base = (void __iomem *)base;
|
||||
pp->base = base;
|
||||
spin_lock_init(&pp->conf_lock);
|
||||
memset(&pp->res, 0, sizeof(pp->res));
|
||||
} else {
|
||||
|
|
@ -249,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
|
|||
|
||||
if (init_port0) {
|
||||
add_pcie_port(0, 0, PCIE00_VIRT_BASE);
|
||||
if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
|
||||
if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
|
||||
add_pcie_port(0, 1, PCIE01_VIRT_BASE);
|
||||
add_pcie_port(0, 2, PCIE02_VIRT_BASE);
|
||||
add_pcie_port(0, 3, PCIE03_VIRT_BASE);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
|
||||
obj-y += system-controller.o
|
||||
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
|
||||
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* Address map functions for Marvell 370 / XP SoCs
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <plat/addr-map.h>
|
||||
|
||||
/*
|
||||
* Generic Address Decode Windows bit settings
|
||||
*/
|
||||
#define ARMADA_XP_TARGET_DEV_BUS 1
|
||||
#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
|
||||
#define ARMADA_XP_TARGET_ETH1 3
|
||||
#define ARMADA_XP_TARGET_PCIE_0_2 4
|
||||
#define ARMADA_XP_TARGET_ETH0 7
|
||||
#define ARMADA_XP_TARGET_PCIE_1_3 8
|
||||
|
||||
#define ARMADA_370_TARGET_DEV_BUS 1
|
||||
#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
|
||||
#define ARMADA_370_TARGET_PCIE_0 4
|
||||
#define ARMADA_370_TARGET_PCIE_1 8
|
||||
|
||||
#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
|
||||
#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
|
||||
|
||||
static const struct __initdata orion_addr_map_info
|
||||
armada_xp_addr_map_info[] = {
|
||||
/*
|
||||
* Window for the BootROM, needed for SMP on Armada XP
|
||||
*/
|
||||
{ 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
|
||||
ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
|
||||
/* End marker */
|
||||
{ -1, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static const struct __initdata orion_addr_map_info
|
||||
armada_370_addr_map_info[] = {
|
||||
/* End marker */
|
||||
{ -1, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct of_device_id of_addr_decoding_controller_table[] = {
|
||||
{ .compatible = "marvell,armada-addr-decoding-controller" },
|
||||
{ /* end of list */ },
|
||||
};
|
||||
|
||||
static void __iomem *
|
||||
armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
|
||||
{
|
||||
unsigned int offset;
|
||||
|
||||
/* The register layout is a bit annoying and the below code
|
||||
* tries to cope with it.
|
||||
* - At offset 0x0, there are the registers for the first 8
|
||||
* windows, with 4 registers of 32 bits per window (ctrl,
|
||||
* base, remap low, remap high)
|
||||
* - Then at offset 0x80, there is a hole of 0x10 bytes for
|
||||
* the internal registers base address and internal units
|
||||
* sync barrier register.
|
||||
* - Then at offset 0x90, there the registers for 12
|
||||
* windows, with only 2 registers of 32 bits per window
|
||||
* (ctrl, base).
|
||||
*/
|
||||
if (win < 8)
|
||||
offset = (win << 4);
|
||||
else
|
||||
offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
|
||||
|
||||
return cfg->bridge_virt_base + offset;
|
||||
}
|
||||
|
||||
static struct __initdata orion_addr_map_cfg addr_map_cfg = {
|
||||
.num_wins = 20,
|
||||
.remappable_wins = 8,
|
||||
.win_cfg_base = armada_cfg_base,
|
||||
};
|
||||
|
||||
static int __init armada_setup_cpu_mbus(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *mbus_unit_addr_decoding_base;
|
||||
void __iomem *sdram_addr_decoding_base;
|
||||
|
||||
np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
mbus_unit_addr_decoding_base = of_iomap(np, 0);
|
||||
BUG_ON(!mbus_unit_addr_decoding_base);
|
||||
|
||||
sdram_addr_decoding_base =
|
||||
mbus_unit_addr_decoding_base +
|
||||
ARMADA_SDRAM_ADDR_DECODING_OFFSET;
|
||||
|
||||
addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
|
||||
|
||||
/*
|
||||
* Disable, clear and configure windows.
|
||||
*/
|
||||
if (of_machine_is_compatible("marvell,armadaxp"))
|
||||
orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
|
||||
else if (of_machine_is_compatible("marvell,armada370"))
|
||||
orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
|
||||
else {
|
||||
pr_err("Unsupported SoC\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup MBUS dram target info.
|
||||
*/
|
||||
orion_setup_cpu_mbus_target(&addr_map_cfg,
|
||||
sdram_addr_decoding_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Using a early_initcall is needed so that this initialization gets
|
||||
* done before the SMP initialization, which requires the BootROM to
|
||||
* be remapped. */
|
||||
early_initcall(armada_setup_cpu_mbus);
|
||||
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
static struct map_desc armada_370_xp_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = ARMADA_370_XP_REGS_VIRT_BASE,
|
||||
.virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
|
||||
.length = ARMADA_370_XP_REGS_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#define __MACH_ARMADA_370_XP_H
|
||||
|
||||
#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
|
||||
#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000
|
||||
#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000)
|
||||
#define ARMADA_370_XP_REGS_SIZE SZ_1M
|
||||
|
||||
#endif /* __MACH_ARMADA_370_XP_H */
|
||||
|
|
|
|||
|
|
@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
|
|||
/*
|
||||
* Setup MBUS dram target info.
|
||||
*/
|
||||
orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
|
||||
orion_setup_cpu_mbus_target(&addr_map_cfg,
|
||||
(void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
|
||||
}
|
||||
|
||||
void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
|
||||
|
|
|
|||
|
|
@ -42,12 +42,12 @@
|
|||
****************************************************************************/
|
||||
static struct map_desc orion5x_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = ORION5X_REGS_VIRT_BASE,
|
||||
.virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
|
||||
.length = ORION5X_REGS_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = ORION5X_PCIE_WA_VIRT_BASE,
|
||||
.virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
|
||||
.length = ORION5X_PCIE_WA_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
|
|
|
|||
|
|
@ -701,7 +701,7 @@ static void __init dns323_init(void)
|
|||
* Note: AFAIK, rev B1 needs the same treatement but I'll let
|
||||
* somebody else test it.
|
||||
*/
|
||||
writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
|
||||
writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,27 +13,27 @@
|
|||
|
||||
#include <mach/orion5x.h>
|
||||
|
||||
#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100)
|
||||
#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
|
||||
|
||||
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
|
||||
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
|
||||
|
||||
#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
|
||||
#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
|
||||
#define WDT_RESET_OUT_EN 0x0002
|
||||
|
||||
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
|
||||
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
|
||||
|
||||
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
|
||||
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
|
||||
|
||||
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
|
||||
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
|
||||
|
||||
#define WDT_INT_REQ 0x0008
|
||||
|
||||
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
||||
|
||||
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
|
||||
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
|
||||
|
||||
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204)
|
||||
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
|
||||
|
||||
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
|
||||
#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300)
|
||||
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
|
||||
#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
* fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
|
||||
****************************************************************************/
|
||||
#define ORION5X_REGS_PHYS_BASE 0xf1000000
|
||||
#define ORION5X_REGS_VIRT_BASE 0xfe000000
|
||||
#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000)
|
||||
#define ORION5X_REGS_SIZE SZ_1M
|
||||
|
||||
#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
|
||||
|
|
@ -53,7 +53,7 @@
|
|||
|
||||
/* Relevant only for Orion-1/Orion-NAS */
|
||||
#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
|
||||
#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000
|
||||
#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
|
||||
#define ORION5X_PCIE_WA_SIZE SZ_16M
|
||||
|
||||
#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
|
||||
|
|
@ -66,42 +66,42 @@
|
|||
* Orion Registers Map
|
||||
******************************************************************************/
|
||||
|
||||
#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
|
||||
#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500)
|
||||
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
|
||||
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
|
||||
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
|
||||
#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
|
||||
#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500)
|
||||
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
|
||||
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
|
||||
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
|
||||
#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
|
||||
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
|
||||
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
|
||||
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
|
||||
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
|
||||
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
|
||||
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
|
||||
#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
|
||||
#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
|
||||
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
|
||||
|
||||
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
|
||||
#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x20000)
|
||||
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
|
||||
#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
|
||||
|
||||
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
|
||||
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
|
||||
|
||||
#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
|
||||
#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000)
|
||||
|
||||
#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
|
||||
#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
|
||||
#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000)
|
||||
#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000)
|
||||
|
||||
#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
|
||||
#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
|
||||
#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900)
|
||||
#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900)
|
||||
|
||||
#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
|
||||
#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
|
||||
#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000)
|
||||
#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000)
|
||||
|
||||
#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
|
||||
#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
|
||||
#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000)
|
||||
#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000)
|
||||
|
||||
#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000)
|
||||
#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000)
|
||||
|
||||
#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
|
||||
#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
|
||||
#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000)
|
||||
#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000)
|
||||
|
||||
/*******************************************************************************
|
||||
* Device Bus Registers
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include <plat/orion-gpio.h>
|
||||
#include <plat/irq.h>
|
||||
|
|
@ -25,11 +26,11 @@ static int __initdata gpio0_irqs[4] = {
|
|||
|
||||
void __init orion5x_init_irq(void)
|
||||
{
|
||||
orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
|
||||
orion_irq_init(0, MAIN_IRQ_MASK);
|
||||
|
||||
/*
|
||||
* Initialize gpiolib for GPIOs 0-31.
|
||||
*/
|
||||
orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0,
|
||||
orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
|
||||
IRQ_ORION5X_GPIO_START, gpio0_irqs);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
/*****************************************************************************
|
||||
* PCIe controller
|
||||
****************************************************************************/
|
||||
#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
|
||||
#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
|
||||
|
||||
void __init orion5x_pcie_id(u32 *dev, u32 *rev)
|
||||
{
|
||||
|
|
@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
|
|||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
|
||||
ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
|
||||
bus, devfn, where, size, val);
|
||||
|
||||
return ret;
|
||||
|
|
@ -188,7 +188,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
|
|||
/*****************************************************************************
|
||||
* PCI controller
|
||||
****************************************************************************/
|
||||
#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
|
||||
#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
|
||||
#define PCI_MODE ORION5X_PCI_REG(0xd00)
|
||||
#define PCI_CMD ORION5X_PCI_REG(0xc00)
|
||||
#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
|
||||
|
|
|
|||
|
|
@ -2,9 +2,8 @@
|
|||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
obj- :=
|
||||
obj-y += addr-map.o
|
||||
|
||||
obj-$(CONFIG_GENERIC_GPIO) += gpio.o
|
||||
orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
|
||||
obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
|
||||
obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y)
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
|
|||
static void __init __iomem *
|
||||
orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
|
||||
{
|
||||
return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
|
||||
return cfg->bridge_virt_base + (win << 4);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
|
|||
* Setup MBUS dram target info.
|
||||
*/
|
||||
void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
|
||||
const u32 ddr_window_cpu_base)
|
||||
const void __iomem *ddr_window_cpu_base)
|
||||
{
|
||||
void __iomem *addr;
|
||||
int i;
|
||||
int cs;
|
||||
|
||||
orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
|
||||
|
||||
addr = (void __iomem *)ddr_window_cpu_base;
|
||||
|
||||
for (i = 0, cs = 0; i < 4; i++) {
|
||||
u32 base = readl(addr + DDR_BASE_CS_OFF(i));
|
||||
u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
|
||||
u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
|
||||
u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
|
||||
|
||||
/*
|
||||
* Chip select enabled?
|
||||
|
|
|
|||
|
|
@ -86,13 +86,13 @@ static void __init uart_complete(
|
|||
struct platform_device *orion_uart,
|
||||
struct plat_serial8250_port *data,
|
||||
struct resource *resources,
|
||||
unsigned int membase,
|
||||
void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk)
|
||||
{
|
||||
data->mapbase = mapbase;
|
||||
data->membase = (void __iomem *)membase;
|
||||
data->membase = membase;
|
||||
data->irq = irq;
|
||||
data->uartclk = uart_get_clk_rate(clk);
|
||||
orion_uart->dev.platform_data = data;
|
||||
|
|
@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
|
|||
.id = PLAT8250_DEV_PLATFORM,
|
||||
};
|
||||
|
||||
void __init orion_uart0_init(unsigned int membase,
|
||||
void __init orion_uart0_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk)
|
||||
|
|
@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
|
|||
.id = PLAT8250_DEV_PLATFORM1,
|
||||
};
|
||||
|
||||
void __init orion_uart1_init(unsigned int membase,
|
||||
void __init orion_uart1_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk)
|
||||
|
|
@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
|
|||
.id = PLAT8250_DEV_PLATFORM2,
|
||||
};
|
||||
|
||||
void __init orion_uart2_init(unsigned int membase,
|
||||
void __init orion_uart2_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk)
|
||||
|
|
@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
|
|||
.id = 3,
|
||||
};
|
||||
|
||||
void __init orion_uart3_init(unsigned int membase,
|
||||
void __init orion_uart3_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
|
|||
struct orion_addr_map_cfg {
|
||||
const int num_wins; /* Total number of windows */
|
||||
const int remappable_wins;
|
||||
const u32 bridge_virt_base;
|
||||
void __iomem *bridge_virt_base;
|
||||
|
||||
/* If NULL, the default cpu_win_can_remap will be used, using
|
||||
the value in remappable_wins */
|
||||
|
|
@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
|
|||
const u8 attr, const int remap);
|
||||
|
||||
void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
|
||||
const u32 ddr_window_cpu_base);
|
||||
const void __iomem *ddr_window_cpu_base);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -13,22 +13,22 @@
|
|||
|
||||
struct dsa_platform_data;
|
||||
|
||||
void __init orion_uart0_init(unsigned int membase,
|
||||
void __init orion_uart0_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk);
|
||||
|
||||
void __init orion_uart1_init(unsigned int membase,
|
||||
void __init orion_uart1_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk);
|
||||
|
||||
void __init orion_uart2_init(unsigned int membase,
|
||||
void __init orion_uart2_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk);
|
||||
|
||||
void __init orion_uart3_init(unsigned int membase,
|
||||
void __init orion_uart3_init(void __iomem *membase,
|
||||
resource_size_t mapbase,
|
||||
unsigned int irq,
|
||||
struct clk *clk);
|
||||
|
|
|
|||
|
|
@ -29,6 +29,6 @@
|
|||
#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1)
|
||||
|
||||
void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
|
||||
unsigned int mpp_max, unsigned int dev_bus);
|
||||
unsigned int mpp_max, void __iomem *dev_bus);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,9 +11,9 @@
|
|||
#ifndef __PLAT_TIME_H
|
||||
#define __PLAT_TIME_H
|
||||
|
||||
void orion_time_set_base(u32 timer_base);
|
||||
void orion_time_set_base(void __iomem *timer_base);
|
||||
|
||||
void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
|
||||
void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
|
||||
unsigned int irq, unsigned int tclk);
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -18,15 +18,15 @@
|
|||
#include <plat/mpp.h>
|
||||
|
||||
/* Address of the ith MPP control register */
|
||||
static __init unsigned long mpp_ctrl_addr(unsigned int i,
|
||||
unsigned long dev_bus)
|
||||
static __init void __iomem *mpp_ctrl_addr(unsigned int i,
|
||||
void __iomem *dev_bus)
|
||||
{
|
||||
return dev_bus + (i) * 4;
|
||||
}
|
||||
|
||||
|
||||
void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
|
||||
unsigned int mpp_max, unsigned int dev_bus)
|
||||
unsigned int mpp_max, void __iomem *dev_bus)
|
||||
{
|
||||
unsigned int mpp_nr_regs = (1 + mpp_max/8);
|
||||
u32 mpp_ctrl[mpp_nr_regs];
|
||||
|
|
|
|||
|
|
@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
|
|||
};
|
||||
|
||||
void __init
|
||||
orion_time_set_base(u32 _timer_base)
|
||||
orion_time_set_base(void __iomem *_timer_base)
|
||||
{
|
||||
timer_base = (void __iomem *)_timer_base;
|
||||
timer_base = _timer_base;
|
||||
}
|
||||
|
||||
void __init
|
||||
orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
|
||||
orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
|
||||
unsigned int irq, unsigned int tclk)
|
||||
{
|
||||
u32 u;
|
||||
|
|
@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
|
|||
/*
|
||||
* Set SoC-specific data.
|
||||
*/
|
||||
bridge_base = (void __iomem *)_bridge_base;
|
||||
bridge_base = _bridge_base;
|
||||
bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
|
||||
|
||||
ticks_per_jiffy = (tclk + HZ/2) / HZ;
|
||||
|
|
|
|||
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