sfc: QT2025C: Switch into self-configure mode when not in loopback
The PHY boots in a mode which is not necessarily optimal. This change switches it to self-configure mode (except when in loopback, which won't work in that mode if an SFP+ module is not present) by rebooting the PHY's microcontroller, and replicating the sequence of configuration writes from the boot EEPROM with the appropriate changes. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matthew Slattery
David S. Miller
Родитель
17d6aeafe9
Коммит
0d83b2f64c
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@ -33,6 +33,9 @@
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#define PCS_FW_HEARTBEAT_REG 0xd7ee
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#define PCS_FW_HEARTB_LBN 0
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#define PCS_FW_HEARTB_WIDTH 8
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#define PCS_FW_PRODUCT_CODE_1 0xd7f0
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#define PCS_FW_VERSION_1 0xd7f3
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#define PCS_FW_BUILD_1 0xd7f6
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#define PCS_UC8051_STATUS_REG 0xd7fd
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#define PCS_UC_STATUS_LBN 0
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#define PCS_UC_STATUS_WIDTH 8
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@ -54,6 +57,7 @@ struct qt202x_phy_data {
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enum efx_phy_mode phy_mode;
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bool bug17190_in_bad_state;
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unsigned long bug17190_timer;
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u32 firmware_ver;
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};
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#define QT2022C2_MAX_RESET_TIME 500
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@ -100,6 +104,25 @@ static int qt2025c_wait_reset(struct efx_nic *efx)
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return 0;
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}
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static void qt2025c_firmware_id(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data = efx->phy_data;
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u8 firmware_id[9];
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size_t i;
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for (i = 0; i < sizeof(firmware_id); i++)
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firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
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PCS_FW_PRODUCT_CODE_1 + i);
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EFX_INFO(efx, "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
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(firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
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firmware_id[3] >> 4, firmware_id[3] & 0xf,
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firmware_id[4], firmware_id[5],
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firmware_id[6], firmware_id[7], firmware_id[8]);
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phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
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((firmware_id[3] & 0x0f) << 16) |
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(firmware_id[4] << 8) | firmware_id[5];
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}
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static void qt2025c_bug17190_workaround(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data = efx->phy_data;
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@ -133,6 +156,95 @@ static void qt2025c_bug17190_workaround(struct efx_nic *efx)
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}
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}
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static int qt2025c_select_phy_mode(struct efx_nic *efx)
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{
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struct qt202x_phy_data *phy_data = efx->phy_data;
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struct falcon_board *board = falcon_board(efx);
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int reg, rc, i;
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uint16_t phy_op_mode;
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/* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
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* Self-Configure mode. Don't attempt any switching if we encounter
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* older firmware. */
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if (phy_data->firmware_ver < 0x02000100)
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return 0;
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/* In general we will get optimal behaviour in "SFP+ Self-Configure"
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* mode; however, that powers down most of the PHY when no module is
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* present, so we must use a different mode (any fixed mode will do)
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* to be sure that loopbacks will work. */
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phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
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/* Only change mode if really necessary */
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reg = efx_mdio_read(efx, 1, 0xc319);
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if ((reg & 0x0038) == phy_op_mode)
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return 0;
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EFX_LOG(efx, "Switching PHY to mode 0x%04x\n", phy_op_mode);
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/* This sequence replicates the register writes configured in the boot
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* EEPROM (including the differences between board revisions), except
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* that the operating mode is changed, and the PHY is prevented from
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* unnecessarily reloading the main firmware image again. */
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efx_mdio_write(efx, 1, 0xc300, 0x0000);
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/* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
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* STOPs onto the firmware/module I2C bus to reset it, varies across
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* board revisions, as the bus is connected to different GPIO/LED
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* outputs on the PHY.) */
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if (board->major == 0 && board->minor < 2) {
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efx_mdio_write(efx, 1, 0xc303, 0x4498);
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for (i = 0; i < 9; i++) {
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efx_mdio_write(efx, 1, 0xc303, 0x4488);
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efx_mdio_write(efx, 1, 0xc303, 0x4480);
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efx_mdio_write(efx, 1, 0xc303, 0x4490);
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efx_mdio_write(efx, 1, 0xc303, 0x4498);
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}
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} else {
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efx_mdio_write(efx, 1, 0xc303, 0x0920);
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efx_mdio_write(efx, 1, 0xd008, 0x0004);
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for (i = 0; i < 9; i++) {
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efx_mdio_write(efx, 1, 0xc303, 0x0900);
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efx_mdio_write(efx, 1, 0xd008, 0x0005);
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efx_mdio_write(efx, 1, 0xc303, 0x0920);
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efx_mdio_write(efx, 1, 0xd008, 0x0004);
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}
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efx_mdio_write(efx, 1, 0xc303, 0x4900);
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}
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efx_mdio_write(efx, 1, 0xc303, 0x4900);
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efx_mdio_write(efx, 1, 0xc302, 0x0004);
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efx_mdio_write(efx, 1, 0xc316, 0x0013);
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efx_mdio_write(efx, 1, 0xc318, 0x0054);
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efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
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efx_mdio_write(efx, 1, 0xc31a, 0x0098);
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efx_mdio_write(efx, 3, 0x0026, 0x0e00);
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efx_mdio_write(efx, 3, 0x0027, 0x0013);
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efx_mdio_write(efx, 3, 0x0028, 0xa528);
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efx_mdio_write(efx, 1, 0xd006, 0x000a);
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efx_mdio_write(efx, 1, 0xd007, 0x0009);
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efx_mdio_write(efx, 1, 0xd008, 0x0004);
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/* This additional write is not present in the boot EEPROM. It
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* prevents the PHY's internal boot ROM doing another pointless (and
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* slow) reload of the firmware image (the microcontroller's code
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* memory is not affected by the microcontroller reset). */
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efx_mdio_write(efx, 1, 0xc317, 0x00ff);
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efx_mdio_write(efx, 1, 0xc300, 0x0002);
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msleep(20);
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/* Restart microcontroller execution from RAM */
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efx_mdio_write(efx, 3, 0xe854, 0x00c0);
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efx_mdio_write(efx, 3, 0xe854, 0x0040);
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msleep(50);
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/* Wait for the microcontroller to be ready again */
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rc = qt2025c_wait_reset(efx);
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if (rc < 0) {
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EFX_ERR(efx, "PHY microcontroller reset during mode switch "
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"timed out\n");
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return rc;
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}
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return 0;
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}
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static int qt202x_reset_phy(struct efx_nic *efx)
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{
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int rc;
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@ -206,6 +318,9 @@ static int qt202x_phy_init(struct efx_nic *efx)
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devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
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efx_mdio_id_rev(devid));
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if (efx->phy_type == PHY_TYPE_QT2025C)
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qt2025c_firmware_id(efx);
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return 0;
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}
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@ -234,6 +349,10 @@ static int qt202x_phy_reconfigure(struct efx_nic *efx)
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struct qt202x_phy_data *phy_data = efx->phy_data;
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if (efx->phy_type == PHY_TYPE_QT2025C) {
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int rc = qt2025c_select_phy_mode(efx);
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if (rc)
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return rc;
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/* There are several different register bits which can
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* disable TX (and save power) on direct-attach cables
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* or optical transceivers, varying somewhat between
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