Renesas ARM Based SoC DT Updates for v3.20
* Use clock-indices instead of deprecated renesas,clock-indices * Prepare for r8a73a4 multiplatform support * Increase clock coverage for r8a779[014] * Correct r8a7779 clock usage * Correct LAN9220 VDDVARIO voltage on ape6evm * Correct QSPI SPI-Flash mode of lager and koelsch * Correct flash partition label and size on koelsch * Correct mask for GIC PPI interrupts on r8a779[14] * Correct BSC bus range on ape6evm-reference -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUoJ1RAAoJENfPZGlqN0+++ugP/iUvSPavdjaBw2poMzIq5UUG z3XwLVTUHOB4fg8vguwzTnu9YyEH9yqqqmRhvdehbc4WvdffjXqAVbVvTChm1DmA kcfEYvGfID198jGBxLJFmFEnr04DiaEtbaLlhh4RpI6MmwmQMR9qiROA3x8fp2TX u4UPgh53VtBxDZAlpKkJyCwcycilNkclrcMOmbBeLy9VV2FKM8nFQmrmwp9AWjyV sBm6vcC2+AeFi7qxxEz7sDsbiDXrDAdDIznQ78ikme46qobpMQagK2EqH/4rfbYI 0rxUlrzcuQlO4jzicpIRZQ9hZYEuYTwFZDcSWyhiNywg7MRd6HqxLoe231jGVu9a kynajAt29g6k35ObbtvWZDSQOnMTSS1fh5kYCgSegZzcjWBSERtMTj/J3UAv62C7 AgBgsN1bFLXQjNyUvf5k863ISVxAJBV4Cdpwe+j38tprWjlVeNNfV9sq0/35OK1h GucAsjaonNh1xfxsAUp4o0OFWSB3q5D/7NyOB2bxE4BwDvImrszaksp+/9bsDJuX mrDdL1WPHv3hAdsp79AO4DkTvNN0k0dOqmJpDn//R2gxZXTkmSEThgjTBixc0t8z jtKw8wucndEtBKYfhR3C3ZvaLoE1QqbUDIRCdGkcUtN/Ezd5dwMql2GoDw0KdfE7 mIqr3Ga6UzjSt5hCu0sw =fZ4r -----END PGP SIGNATURE----- Merge tag 'renesas-dt-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Renesas ARM Based SoC DT Updates for v3.20" from Simon Horman: * Use clock-indices instead of deprecated renesas,clock-indices * Prepare for r8a73a4 multiplatform support * Increase clock coverage for r8a779[014] * Correct r8a7779 clock usage * Correct LAN9220 VDDVARIO voltage on ape6evm * Correct QSPI SPI-Flash mode of lager and koelsch * Correct flash partition label and size on koelsch * Correct mask for GIC PPI interrupts on r8a779[14] * Correct BSC bus range on ape6evm-reference * tag 'renesas-dt-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (30 commits) ARM: shmobile: r8a7791: add MLB+ clock ARM: shmobile: r8a7790: add MLB+ clock ARM: shmobile: ape6evm: Fix LAN9220 VDDVARIO voltage ARM: shmobile: r8a73a4: Add r8a73a4-ape6evm.dtb to ARCH_SHMOBILE_MULTI ARM: shmobile: ape6evm: Add keypad to the device tree ARM: shmobile: ape6evm: Add LEDs to the device tree ARM: shmobile: ape6evm: synchronize dts with reference platform ARM: shmobile: ape6evm: fix compatible string for Ethernet controller ARM: shmobile: r8a7794: Add MMCIF clock to device tree ARM: shmobile: r8a7794: Add SDHI clocks to device tree ARM: shmobile: r8a7794: Add I2C clocks to device tree ARM: shmobile: r8a7779: Add TWD device to DTS ARM: shmobile: r8a7779: Use MSTP for SCIF clocks ARM: shmobile: r8a7779: Use R8A7779_CLK_P as SCIF parent clock ARM: shmobile: r8a7794: Add QSPI clock to device tree ARM: shmobile: lager: Fix QSPI mode of SPI-Flash into mode3 ARM: shmobile: r8a7794: Add SYS-DMAC clocks to device tree ARM: shmobile: r8a7791: Add IPMMU-SGX clock to device tree ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3 ARM: shmobile: r8a7794: Add USBDMAC[01] clocks to device tree ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
0dc4849528
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@ -416,6 +416,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
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sh73a0-kzm9g-reference.dtb
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dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
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r7s72100-genmai.dtb \
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r8a73a4-ape6evm.dtb \
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r8a7740-armadillo800eva.dtb \
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r8a7779-marzen.dtb \
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r8a7790-lager.dtb \
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@ -67,7 +67,7 @@
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x80000000>;
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ranges = <0 0 0 0x20000000>;
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};
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};
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@ -10,14 +10,20 @@
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/dts-v1/;
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#include "r8a73a4.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "APE6EVM";
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compatible = "renesas,ape6evm", "renesas,r8a73a4";
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aliases {
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serial0 = &scifa0;
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};
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chosen {
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bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
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stdout-path = &scifa0;
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};
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memory@40000000 {
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@ -30,7 +36,35 @@
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reg = <2 0x00000000 0 0x40000000>;
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};
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ape6evm_fixed_3v3: fixedregulator@0 {
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vcc_mmc0: regulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "MMC0 Vcc";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-always-on;
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};
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vcc_sdhi0: regulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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/* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */
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ape6evm_fixed_1v8: regulator@2 {
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compatible = "regulator-fixed";
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regulator-name = "1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ape6evm_fixed_3v3: regulator@3 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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@ -39,11 +73,13 @@
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};
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lbsc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x20000000>;
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ethernet@8000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x08000000 0x1000>;
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interrupt-parent = <&irqc1>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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@ -52,7 +88,75 @@
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smsc,irq-active-high;
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smsc,irq-push-pull;
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vdd33a-supply = <&ape6evm_fixed_3v3>;
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vddvario-supply = <&ape6evm_fixed_3v3>;
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vddvario-supply = <&ape6evm_fixed_1v8>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led1 {
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gpios = <&pfc 28 GPIO_ACTIVE_LOW>;
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label = "GNSS_EN";
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};
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led2 {
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gpios = <&pfc 126 GPIO_ACTIVE_LOW>;
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label = "NFC_NRST";
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};
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led3 {
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gpios = <&pfc 132 GPIO_ACTIVE_LOW>;
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label = "GNSS_NRST";
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};
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led4 {
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gpios = <&pfc 232 GPIO_ACTIVE_LOW>;
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label = "BT_WAKEUP";
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};
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led5 {
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gpios = <&pfc 250 GPIO_ACTIVE_LOW>;
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label = "STROBE";
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};
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led6 {
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gpios = <&pfc 288 GPIO_ACTIVE_LOW>;
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label = "BBRESETOUT";
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};
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};
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keyboard {
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compatible = "gpio-keys";
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zero-key {
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gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_0>;
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label = "S16";
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};
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menu-key {
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gpios = <&pfc 325 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_MENU>;
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label = "S17";
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};
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home-key {
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gpios = <&pfc 326 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_HOME>;
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label = "S18";
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};
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back-key {
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gpios = <&pfc 327 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_BACK>;
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label = "S19";
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};
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volup-key {
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gpios = <&pfc 328 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEUP>;
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label = "S20";
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};
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voldown-key {
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gpios = <&pfc 329 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEDOWN>;
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label = "S21";
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};
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};
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};
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@ -79,3 +183,64 @@
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>;
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voltage-tolerance = <1>; /* 1% */
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};
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&cmt1 {
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status = "okay";
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};
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&pfc {
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scifa0_pins: serial0 {
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renesas,groups = "scifa0_data";
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renesas,function = "scifa0";
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};
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mmc0_pins: mmc {
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renesas,groups = "mmc0_data8", "mmc0_ctrl";
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renesas,function = "mmc0";
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};
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sdhi0_pins: sd0 {
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renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
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renesas,function = "sdhi0";
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};
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sdhi1_pins: sd1 {
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renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
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renesas,function = "sdhi1";
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};
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};
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&mmcif0 {
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vmmc-supply = <&vcc_mmc0>;
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "okay";
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};
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&scifa0 {
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pinctrl-0 = <&scifa0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi0 {
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vmmc-supply = <&vcc_sdhi0>;
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bus-width = <4>;
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toshiba,mmc-wrprotect-disable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdhi0_pins>;
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status = "okay";
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};
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&sdhi1 {
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vmmc-supply = <&ape6evm_fixed_3v3>;
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bus-width = <4>;
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broken-cd;
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toshiba,mmc-wrprotect-disable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdhi1_pins>;
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status = "okay";
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};
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@ -453,7 +453,7 @@
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reg = <0xe6150080 4>;
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clocks = <&sub_clk>, <&sub_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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clock-indices = <
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R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
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>;
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clock-output-names =
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@ -468,7 +468,7 @@
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<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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clock-indices = <
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R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
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R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
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R8A7740_CLK_LCDC0
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@ -489,7 +489,7 @@
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<&sub_clk>, <&sub_clk>, <&sub_clk>,
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<&sub_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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clock-indices = <
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R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
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R8A7740_CLK_SCIFA7
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R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
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@ -518,7 +518,7 @@
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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clock-indices = <
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R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
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R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
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R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
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@ -535,7 +535,7 @@
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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clock-indices = <
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R8A7740_CLK_USBH R8A7740_CLK_SDHI2
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R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
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>;
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@ -12,6 +12,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7779-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -62,6 +63,14 @@
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<0xf0000100 0x100>;
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};
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timer@f0000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xf0000600 0x20>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg_clocks R8A7779_CLK_ZS>;
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};
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gpio0: gpio@ffc40000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc40000 0x2c>;
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@ -200,7 +209,7 @@
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe40000 0x100>;
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interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -209,7 +218,7 @@
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe41000 0x100>;
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interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -218,7 +227,7 @@
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe42000 0x100>;
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interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -227,7 +236,7 @@
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe43000 0x100>;
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interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -236,7 +245,7 @@
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe44000 0x100>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -245,7 +254,7 @@
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe45000 0x100>;
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interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -464,18 +473,18 @@
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S1>,
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||||
<&cpg_clocks R8A7779_CLK_S1>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_P>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
|
||||
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
|
||||
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
|
||||
|
|
@ -506,7 +515,7 @@
|
|||
<&cpg_clocks R8A7779_CLK_P>,
|
||||
<&cpg_clocks R8A7779_CLK_S>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7779_CLK_USB01 R8A7779_CLK_USB2
|
||||
R8A7779_CLK_DU R8A7779_CLK_VIN2
|
||||
R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
|
||||
|
|
@ -527,7 +536,7 @@
|
|||
clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
|
||||
<&s4_clk>, <&s4_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
|
||||
R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
|
||||
R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
|
||||
|
|
|
|||
|
|
@ -397,6 +397,8 @@
|
|||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
m25p,fast-read;
|
||||
|
||||
partition@0 {
|
||||
|
|
|
|||
|
|
@ -1054,7 +1054,7 @@
|
|||
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
||||
clocks = <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
|
||||
clock-indices = <R8A7790_CLK_MSIOF0>;
|
||||
clock-output-names = "msiof0";
|
||||
};
|
||||
mstp1_clks: mstp1_clks@e6150134 {
|
||||
|
|
@ -1065,7 +1065,7 @@
|
|||
<&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
|
||||
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
|
||||
R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
|
||||
R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
|
||||
|
|
@ -1087,7 +1087,7 @@
|
|||
<&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
|
||||
<&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
|
||||
R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
|
||||
R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
|
||||
|
|
@ -1106,7 +1106,7 @@
|
|||
<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
|
||||
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
|
||||
R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
|
||||
|
|
@ -1123,8 +1123,10 @@
|
|||
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
||||
clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
|
||||
R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
|
||||
clock-indices = <
|
||||
R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
|
||||
R8A7790_CLK_THERMAL R8A7790_CLK_PWM
|
||||
>;
|
||||
clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
|
||||
};
|
||||
mstp7_clks: mstp7_clks@e615014c {
|
||||
|
|
@ -1134,7 +1136,7 @@
|
|||
<&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
|
||||
<&zx_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
|
||||
R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
|
||||
R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
|
||||
|
|
@ -1147,16 +1149,17 @@
|
|||
mstp8_clks: mstp8_clks@e6150990 {
|
||||
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
||||
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
|
||||
<&zs_clk>, <&zs_clk>;
|
||||
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
|
||||
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
|
||||
R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
|
||||
R8A7790_CLK_SATA0
|
||||
clock-indices = <
|
||||
R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
|
||||
R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
|
||||
R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
|
||||
>;
|
||||
clock-output-names =
|
||||
"vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
|
||||
"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
|
||||
"sata1", "sata0";
|
||||
};
|
||||
mstp9_clks: mstp9_clks@e6150994 {
|
||||
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
|
|
@ -1166,7 +1169,7 @@
|
|||
<&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
|
||||
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
|
||||
R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
|
||||
R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
|
||||
|
|
|
|||
|
|
@ -444,6 +444,8 @@
|
|||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
m25p,fast-read;
|
||||
|
||||
partition@0 {
|
||||
|
|
@ -452,13 +454,13 @@
|
|||
read-only;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "bootenv";
|
||||
reg = <0x00080000 0x00080000>;
|
||||
label = "user";
|
||||
reg = <0x00080000 0x00580000>;
|
||||
read-only;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "data";
|
||||
reg = <0x00100000 0x03f00000>;
|
||||
partition@600000 {
|
||||
label = "flash";
|
||||
reg = <0x00600000 0x03a00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@
|
|||
<0 0xf1002000 0 0x1000>,
|
||||
<0 0xf1004000 0 0x2000>,
|
||||
<0 0xf1006000 0 0x2000>;
|
||||
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
|
|
@ -186,10 +186,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
cmt0: timer@ffca0000 {
|
||||
|
|
@ -1062,7 +1062,7 @@
|
|||
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
||||
clocks = <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
|
||||
clock-indices = <R8A7791_CLK_MSIOF0>;
|
||||
clock-output-names = "msiof0";
|
||||
};
|
||||
mstp1_clks: mstp1_clks@e6150134 {
|
||||
|
|
@ -1073,7 +1073,7 @@
|
|||
<&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
|
||||
<&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
|
||||
R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
|
||||
R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
|
||||
|
|
@ -1093,7 +1093,7 @@
|
|||
<&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
|
||||
R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
|
||||
R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
|
||||
|
|
@ -1111,7 +1111,7 @@
|
|||
<&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
|
||||
R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
|
||||
R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
|
||||
|
|
@ -1127,8 +1127,10 @@
|
|||
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
||||
clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
|
||||
R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
|
||||
clock-indices = <
|
||||
R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
|
||||
R8A7791_CLK_THERMAL R8A7791_CLK_PWM
|
||||
>;
|
||||
clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
|
||||
};
|
||||
mstp7_clks: mstp7_clks@e615014c {
|
||||
|
|
@ -1138,7 +1140,7 @@
|
|||
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
||||
<&zx_clk>, <&zx_clk>, <&zx_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
|
||||
R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
|
||||
R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
|
||||
|
|
@ -1152,15 +1154,17 @@
|
|||
mstp8_clks: mstp8_clks@e6150990 {
|
||||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
||||
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
|
||||
<&zs_clk>;
|
||||
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
|
||||
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
|
||||
R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
|
||||
R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
|
||||
>;
|
||||
clock-output-names =
|
||||
"vin2", "vin1", "vin0", "ether", "sata1", "sata0";
|
||||
"ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
|
||||
"sata1", "sata0";
|
||||
};
|
||||
mstp9_clks: mstp9_clks@e6150994 {
|
||||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
|
|
@ -1171,7 +1175,7 @@
|
|||
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
|
||||
R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
|
||||
R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
|
||||
|
|
@ -1221,7 +1225,7 @@
|
|||
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
|
||||
>;
|
||||
clock-output-names = "scifa3", "scifa4", "scifa5";
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
<0 0xf1002000 0 0x1000>,
|
||||
<0 0xf1004000 0 0x2000>,
|
||||
<0 0xf1006000 0 0x2000>;
|
||||
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
cmt0: timer@ffca0000 {
|
||||
|
|
@ -84,10 +84,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
irqc0: interrupt-controller@e61c0000 {
|
||||
|
|
@ -293,6 +293,28 @@
|
|||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z";
|
||||
};
|
||||
/* Variable factor clocks */
|
||||
sd1_clk: sd2_clk@e6150078 {
|
||||
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150078 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd1";
|
||||
};
|
||||
sd2_clk: sd3_clk@e615007c {
|
||||
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615007c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
};
|
||||
mmc0_clk: mmc0_clk@e6150240 {
|
||||
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150240 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
|
|
@ -455,7 +477,7 @@
|
|||
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
||||
clocks = <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
|
||||
clock-indices = <R8A7794_CLK_MSIOF0>;
|
||||
clock-output-names = "msiof0";
|
||||
};
|
||||
mstp1_clks: mstp1_clks@e6150134 {
|
||||
|
|
@ -465,7 +487,7 @@
|
|||
<&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
|
||||
<&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
|
||||
R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
|
||||
R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
|
||||
|
|
@ -479,41 +501,51 @@
|
|||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&mp_clk>, <&mp_clk>, <&mp_clk>;
|
||||
<&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
|
||||
R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
|
||||
R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
|
||||
R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
||||
"scifb1", "msiof1", "scifb2";
|
||||
"scifb1", "msiof1", "scifb2",
|
||||
"sys-dmac1", "sys-dmac0";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&rclk_clk>;
|
||||
clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
|
||||
<&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
R8A7794_CLK_CMT1
|
||||
clock-indices = <
|
||||
R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
|
||||
R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
|
||||
R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
|
||||
>;
|
||||
clock-output-names =
|
||||
"cmt1";
|
||||
"sdhi2", "sdhi1", "sdhi0",
|
||||
"mmcif0", "cmt1", "usbdmac0", "usbdmac1";
|
||||
};
|
||||
mstp7_clks: mstp7_clks@e615014c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
||||
clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
||||
clocks = <&mp_clk>, <&mp_clk>,
|
||||
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
||||
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
|
||||
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
|
||||
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
|
||||
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
|
||||
R8A7794_CLK_SCIF0
|
||||
>;
|
||||
clock-output-names =
|
||||
"ehci", "hsusb",
|
||||
"hscif2", "scif5", "scif4", "hscif1", "hscif0",
|
||||
"scif3", "scif2", "scif1", "scif0";
|
||||
};
|
||||
|
|
@ -522,18 +554,32 @@
|
|||
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
||||
clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
|
||||
>;
|
||||
clock-output-names =
|
||||
"vin1", "vin0", "ether";
|
||||
};
|
||||
mstp9_clks: mstp9_clks@e6150994 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
||||
clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
|
||||
R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
|
||||
R8A7794_CLK_I2C0
|
||||
>;
|
||||
clock-output-names =
|
||||
"qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
|
||||
};
|
||||
mstp11_clks: mstp11_clks@e615099c {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
|
||||
>;
|
||||
clock-output-names = "scifa3", "scifa4", "scifa5";
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@
|
|||
#define R8A7790_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7790_CLK_MLB 2
|
||||
#define R8A7790_CLK_VIN3 8
|
||||
#define R8A7790_CLK_VIN2 9
|
||||
#define R8A7790_CLK_VIN1 10
|
||||
|
|
|
|||
|
|
@ -91,6 +91,8 @@
|
|||
#define R8A7791_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7791_CLK_IPMMU_SGX 0
|
||||
#define R8A7791_CLK_MLB 2
|
||||
#define R8A7791_CLK_VIN2 9
|
||||
#define R8A7791_CLK_VIN1 10
|
||||
#define R8A7791_CLK_VIN0 11
|
||||
|
|
|
|||
|
|
@ -48,15 +48,25 @@
|
|||
#define R8A7794_CLK_SCIFB1 7
|
||||
#define R8A7794_CLK_MSIOF1 8
|
||||
#define R8A7794_CLK_SCIFB2 16
|
||||
#define R8A7794_CLK_SYS_DMAC1 18
|
||||
#define R8A7794_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7794_CLK_SDHI2 11
|
||||
#define R8A7794_CLK_SDHI1 12
|
||||
#define R8A7794_CLK_SDHI0 14
|
||||
#define R8A7794_CLK_MMCIF0 15
|
||||
#define R8A7794_CLK_CMT1 29
|
||||
#define R8A7794_CLK_USBDMAC0 30
|
||||
#define R8A7794_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7794_CLK_THERMAL 22
|
||||
#define R8A7794_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7794_CLK_EHCI 3
|
||||
#define R8A7794_CLK_HSUSB 4
|
||||
#define R8A7794_CLK_HSCIF2 13
|
||||
#define R8A7794_CLK_SCIF5 14
|
||||
#define R8A7794_CLK_SCIF4 15
|
||||
|
|
@ -80,6 +90,13 @@
|
|||
#define R8A7794_CLK_GPIO2 10
|
||||
#define R8A7794_CLK_GPIO1 11
|
||||
#define R8A7794_CLK_GPIO0 12
|
||||
#define R8A7794_CLK_QSPI_MOD 17
|
||||
#define R8A7794_CLK_I2C5 25
|
||||
#define R8A7794_CLK_I2C4 27
|
||||
#define R8A7794_CLK_I2C3 28
|
||||
#define R8A7794_CLK_I2C2 29
|
||||
#define R8A7794_CLK_I2C1 30
|
||||
#define R8A7794_CLK_I2C0 31
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7794_CLK_SCIFA3 6
|
||||
|
|
|
|||
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