clk: rockchip: switch to using the new cpuclk type for armclk
This adds the necessary soc-specific divider values and switches the armclk to use the newly introduced cpuclk type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
This commit is contained in:
Heiko Stuebner
Родитель
f6fba5f696
Коммит
0e5bdb3f9f
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@ -101,6 +101,98 @@ struct rockchip_pll_rate_table rk3188_pll_rates[] = {
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{ /* sentinel */ },
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};
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#define RK3066_DIV_CORE_PERIPH_MASK 0x3
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#define RK3066_DIV_CORE_PERIPH_SHIFT 6
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#define RK3066_DIV_ACLK_CORE_MASK 0x7
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#define RK3066_DIV_ACLK_CORE_SHIFT 0
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#define RK3066_DIV_ACLK_HCLK_MASK 0x3
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#define RK3066_DIV_ACLK_HCLK_SHIFT 8
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#define RK3066_DIV_ACLK_PCLK_MASK 0x3
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#define RK3066_DIV_ACLK_PCLK_SHIFT 12
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#define RK3066_DIV_AHB2APB_MASK 0x3
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#define RK3066_DIV_AHB2APB_SHIFT 14
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#define RK3066_CLKSEL0(_core_peri) \
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{ \
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.reg = RK2928_CLKSEL_CON(0), \
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.val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
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RK3066_DIV_CORE_PERIPH_SHIFT) \
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}
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#define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \
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{ \
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.reg = RK2928_CLKSEL_CON(1), \
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.val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
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RK3066_DIV_ACLK_CORE_SHIFT) | \
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HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
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RK3066_DIV_ACLK_HCLK_SHIFT) | \
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HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
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RK3066_DIV_ACLK_PCLK_SHIFT) | \
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HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
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RK3066_DIV_AHB2APB_SHIFT), \
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}
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#define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
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{ \
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.prate = _prate, \
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.divs = { \
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RK3066_CLKSEL0(_core_peri), \
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RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \
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}, \
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}
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static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
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RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
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RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
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RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
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RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
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RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
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RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
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RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
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};
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static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
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.core_reg = RK2928_CLKSEL_CON(0),
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.div_core_shift = 0,
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.div_core_mask = 0x1f,
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.mux_core_shift = 8,
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};
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#define RK3188_DIV_ACLK_CORE_MASK 0x7
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#define RK3188_DIV_ACLK_CORE_SHIFT 3
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#define RK3188_CLKSEL1(_aclk_core) \
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{ \
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.reg = RK2928_CLKSEL_CON(1), \
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.val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
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RK3188_DIV_ACLK_CORE_SHIFT) \
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}
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#define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \
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{ \
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.prate = _prate, \
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.divs = { \
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RK3066_CLKSEL0(_core_peri), \
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RK3188_CLKSEL1(_aclk_core), \
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}, \
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}
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static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
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RK3188_CPUCLK_RATE(1608000000, 2, 3),
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RK3188_CPUCLK_RATE(1416000000, 2, 3),
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RK3188_CPUCLK_RATE(1200000000, 2, 3),
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RK3188_CPUCLK_RATE(1008000000, 2, 3),
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RK3188_CPUCLK_RATE( 816000000, 2, 3),
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RK3188_CPUCLK_RATE( 600000000, 1, 3),
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RK3188_CPUCLK_RATE( 504000000, 1, 3),
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RK3188_CPUCLK_RATE( 312000000, 0, 1),
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};
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static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
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.core_reg = RK2928_CLKSEL_CON(0),
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.div_core_shift = 9,
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.div_core_mask = 0x1f,
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.mux_core_shift = 8,
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};
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PNAME(mux_pll_p) = { "xin24m", "xin32k" };
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PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
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PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
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@ -406,8 +498,6 @@ static struct clk_div_table div_aclk_cpu_t[] = {
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};
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static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
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COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
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RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 0, 5, DFLAGS),
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DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
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RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
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DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
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@ -528,8 +618,6 @@ PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1",
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"gpll", "cpll" };
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static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
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COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
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RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 9, 5, DFLAGS),
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COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
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RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
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div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
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@ -657,6 +745,10 @@ static void __init rk3066a_clk_init(struct device_node *np)
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RK3066_GRF_SOC_STATUS);
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rockchip_clk_register_branches(rk3066a_clk_branches,
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ARRAY_SIZE(rk3066a_clk_branches));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3066_cpuclk_data, rk3066_cpuclk_rates,
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ARRAY_SIZE(rk3066_cpuclk_rates));
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}
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CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
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@ -672,6 +764,10 @@ static void __init rk3188a_clk_init(struct device_node *np)
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RK3188_GRF_SOC_STATUS);
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rockchip_clk_register_branches(rk3188_clk_branches,
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ARRAY_SIZE(rk3188_clk_branches));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3188_cpuclk_data, rk3188_cpuclk_rates,
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ARRAY_SIZE(rk3188_cpuclk_rates));
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/* reparent aclk_cpu_pre from apll */
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clk1 = __clk_lookup("aclk_cpu_pre");
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@ -101,6 +101,70 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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{ /* sentinel */ },
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};
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#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
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#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
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#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
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#define RK3288_DIV_ACLK_CORE_MP_SHIFT 4
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#define RK3288_DIV_L2RAM_MASK 0x7
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#define RK3288_DIV_L2RAM_SHIFT 0
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#define RK3288_DIV_ATCLK_MASK 0x1f
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#define RK3288_DIV_ATCLK_SHIFT 4
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#define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f
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#define RK3288_DIV_PCLK_DBGPRE_SHIFT 9
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#define RK3288_CLKSEL0(_core_m0, _core_mp) \
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{ \
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.reg = RK3288_CLKSEL_CON(0), \
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.val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
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RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
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HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
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RK3288_DIV_ACLK_CORE_MP_SHIFT), \
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}
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#define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \
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{ \
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.reg = RK3288_CLKSEL_CON(37), \
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.val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
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RK3288_DIV_L2RAM_SHIFT) | \
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HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
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RK3288_DIV_ATCLK_SHIFT) | \
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HIWORD_UPDATE(_pclk_dbg_pre, \
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RK3288_DIV_PCLK_DBGPRE_MASK, \
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RK3288_DIV_PCLK_DBGPRE_SHIFT), \
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}
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#define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
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{ \
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.prate = _prate, \
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.divs = { \
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RK3288_CLKSEL0(_core_m0, _core_mp), \
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RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \
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}, \
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}
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static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
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RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
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RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
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};
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static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
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.core_reg = RK3288_CLKSEL_CON(0),
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.div_core_shift = 8,
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.div_core_mask = 0x1f,
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.mux_core_shift = 15,
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};
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PNAME(mux_pll_p) = { "xin24m", "xin32k" };
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PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
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PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
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@ -166,8 +230,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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RK3288_CLKGATE_CON(0), 1, GFLAGS),
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GATE(0, "gpll_core", "gpll", 0,
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RK3288_CLKGATE_CON(0), 2, GFLAGS),
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COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
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RK3288_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
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COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
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RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
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@ -739,6 +801,11 @@ static void __init rk3288_clk_init(struct device_node *np)
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rockchip_clk_protect_critical(rk3288_critical_clocks,
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ARRAY_SIZE(rk3288_critical_clocks));
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rockchip_clk_register_armclk(ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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&rk3288_cpuclk_data, rk3288_cpuclk_rates,
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ARRAY_SIZE(rk3288_cpuclk_rates));
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rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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}
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