Our usual number of patches to improve the Allwinner Device Tree
support, including: - Support for the IOMMU on the H6 - Support for cpufreq / thermal throttling on the H6 - Support for the mailbox on the A64, A83t, H3, H5 and H6 - New boards: A20-OLinuXino-LIME-eMMC -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXr7NHgAKCRDj7w1vZxhR xbhGAQCDavHkpjvq4Hwk/znoS0Y6NvW1JQUyKUWH8K6ah1ZkFwEA5gC0Ac9cbDAk Q5fZeYl7mPbEL9DI0RphVqHmY2ezXw0= =WR5/ -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual number of patches to improve the Allwinner Device Tree support, including: - Support for the IOMMU on the H6 - Support for cpufreq / thermal throttling on the H6 - Support for the mailbox on the A64, A83t, H3, H5 and H6 - New boards: A20-OLinuXino-LIME-eMMC * tag 'sunxi-dt-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (23 commits) arm64: dts: allwinner: h6: Add IOMMU arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6 arm64: dts: allwinner: h6: add voltage range to OPP table arm64: dts: allwinner: sun50i-a64: Add missing address/size-cells arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64 arm64: dts: allwinner: Sort Pine H64 device-tree nodes arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3 arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1 arm64: dts: allwinner: h6: Add CPU Operating Performance Points table arm64: dts: allwinner: h6: Add thermal trip points/cooling map arm64: dts: allwinner: h6: Add clock to CPU cores arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI combo module arm64: dts: allwinner: h6: orangepi: Disable OTG mode arm64: dts: allwinner: h6: orangepi: Add gpio power supply ARM: dts: sun8i-h2-plus-bananapi-m2-zero: Fix led polarity arm64: dts: allwinner: h6: Add msgbox node arm64: dts: allwinner: a64: Add msgbox node ARM: dts: sunxi: h3/h5: Add msgbox node ARM: dts: sunxi: a83t: Add msgbox node ARM: dts: sun8i-h3: add opp table for mali gpu ... Link: https://lore.kernel.org/r/cfa66bd9-f74c-4614-9ea5-9ef8546cc571.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
0e909f1861
|
|
@ -561,6 +561,11 @@ properties:
|
|||
- const: olimex,a20-olinuxino-lime
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||||
- const: allwinner,sun7i-a20
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||||
- description: Olimex A20-OlinuXino LIME (with eMMC)
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||||
items:
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||||
- const: olimex,a20-olinuxino-lime-emmc
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||||
- const: allwinner,sun7i-a20
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||||
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||||
- description: Olimex A20-OlinuXino LIME2
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||||
items:
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||||
- const: olimex,a20-olinuxino-lime2
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||||
|
|
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|||
|
|
@ -1121,6 +1121,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
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sun7i-a20-olimex-som204-evb.dtb \
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sun7i-a20-olimex-som204-evb-emmc.dtb \
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sun7i-a20-olinuxino-lime.dtb \
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sun7i-a20-olinuxino-lime-emmc.dtb \
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sun7i-a20-olinuxino-lime2.dtb \
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sun7i-a20-olinuxino-lime2-emmc.dtb \
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sun7i-a20-olinuxino-micro.dtb \
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|
|
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2020 Olimex Ltd.
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* Author: Stefan Mavrodiev <stefan@olimex.com>
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*/
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#include "sun7i-a20-olinuxino-lime.dts"
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/ {
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model = "Olimex A20-OLinuXino-LIME-eMMC";
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compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20";
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||||
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||||
mmc2_pwrseq: pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
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||||
};
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};
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&mmc2 {
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vmmc-supply = <®_vcc3v3>;
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vqmmc-supply = <®_vcc3v3>;
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bus-width = <4>;
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non-removable;
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mmc-pwrseq = <&mmc2_pwrseq>;
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status = "okay";
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emmc: emmc@0 {
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reg = <0>;
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compatible = "mmc-card";
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broken-hpi;
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||||
};
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||||
};
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|
@ -610,6 +610,16 @@
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clock-names = "bus", "mod";
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};
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msgbox: mailbox@1c17000 {
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compatible = "allwinner,sun8i-a83t-msgbox",
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"allwinner,sun6i-a31-msgbox";
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reg = <0x01c17000 0x1000>;
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clocks = <&ccu CLK_BUS_MSGBOX>;
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resets = <&ccu RST_BUS_MSGBOX>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};
|
||||
|
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usb_otg: usb@1c19000 {
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compatible = "allwinner,sun8i-a83t-musb",
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"allwinner,sun8i-a33-musb";
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||||
|
|
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|||
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@ -31,7 +31,7 @@
|
|||
|
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pwr_led {
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label = "bananapi-m2-zero:red:pwr";
|
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
|
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gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
|
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default-state = "on";
|
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};
|
||||
};
|
||||
|
|
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|||
|
|
@ -112,6 +112,26 @@
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|||
};
|
||||
};
|
||||
|
||||
gpu_opp_table: gpu-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
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opp-120000000 {
|
||||
opp-hz = /bits/ 64 <120000000>;
|
||||
};
|
||||
|
||||
opp-312000000 {
|
||||
opp-hz = /bits/ 64 <312000000>;
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};
|
||||
|
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opp-432000000 {
|
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opp-hz = /bits/ 64 <432000000>;
|
||||
};
|
||||
|
||||
opp-576000000 {
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opp-hz = /bits/ 64 <576000000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
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||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -205,9 +225,7 @@
|
|||
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
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clock-names = "bus", "core";
|
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resets = <&ccu RST_BUS_GPU>;
|
||||
|
||||
assigned-clocks = <&ccu CLK_GPU>;
|
||||
assigned-clock-rates = <384000000>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
};
|
||||
|
||||
ths: thermal-sensor@1c25000 {
|
||||
|
|
|
|||
|
|
@ -239,6 +239,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
msgbox: mailbox@1c17000 {
|
||||
compatible = "allwinner,sun8i-h3-msgbox",
|
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"allwinner,sun6i-a31-msgbox";
|
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reg = <0x01c17000 0x1000>;
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||||
clocks = <&ccu CLK_BUS_MSGBOX>;
|
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resets = <&ccu RST_BUS_MSGBOX>;
|
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
usb_otg: usb@1c19000 {
|
||||
compatible = "allwinner,sun8i-h3-musb";
|
||||
reg = <0x01c19000 0x400>;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
label = "a64-olinuxino:red:user";
|
||||
gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
|
||||
};
|
||||
};
|
||||
|
||||
reg_usb1_vbus: usb1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1-vbus";
|
||||
|
|
|
|||
|
|
@ -557,6 +557,16 @@
|
|||
resets = <&ccu RST_BUS_CE>;
|
||||
};
|
||||
|
||||
msgbox: mailbox@1c17000 {
|
||||
compatible = "allwinner,sun50i-a64-msgbox",
|
||||
"allwinner,sun6i-a31-msgbox";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_MSGBOX>;
|
||||
resets = <&ccu RST_BUS_MSGBOX>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
usb_otg: usb@1c19000 {
|
||||
compatible = "allwinner,sun8i-a33-musb";
|
||||
reg = <0x01c19000 0x0400>;
|
||||
|
|
@ -1083,6 +1093,8 @@
|
|||
compatible = "allwinner,sun50i-a64-mbus";
|
||||
reg = <0x01c62000 0x1000>;
|
||||
clocks = <&ccu 112>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sun50i-h6.dtsi"
|
||||
#include "sun50i-h6-cpu-opp.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -77,6 +78,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <®_dcdca>;
|
||||
};
|
||||
|
||||
&de {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -234,7 +239,8 @@
|
|||
reg_dcdca: dcdca {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <810000>;
|
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regulator-max-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <1160000>;
|
||||
regulator-ramp-delay = <2500>;
|
||||
regulator-name = "vdd-cpu";
|
||||
};
|
||||
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||||
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|
@ -242,6 +248,7 @@
|
|||
regulator-enable-ramp-delay = <32000>;
|
||||
regulator-min-microvolt = <810000>;
|
||||
regulator-max-microvolt = <1080000>;
|
||||
regulator-ramp-delay = <2500>;
|
||||
regulator-name = "vdd-gpu";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,117 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
|
||||
// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
|
||||
|
||||
/ {
|
||||
cpu_opp_table: cpu-opp-table {
|
||||
compatible = "allwinner,sun50i-h6-operating-points";
|
||||
nvmem-cells = <&cpu_speed_grade>;
|
||||
opp-shared;
|
||||
|
||||
opp@480000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000 880000 1200000>;
|
||||
opp-microvolt-speed1 = <820000 820000 1200000>;
|
||||
opp-microvolt-speed2 = <820000 820000 1200000>;
|
||||
};
|
||||
|
||||
opp@720000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000 880000 1200000>;
|
||||
opp-microvolt-speed1 = <820000 820000 1200000>;
|
||||
opp-microvolt-speed2 = <820000 820000 1200000>;
|
||||
};
|
||||
|
||||
opp@816000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <816000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000 880000 1200000>;
|
||||
opp-microvolt-speed1 = <820000 820000 1200000>;
|
||||
opp-microvolt-speed2 = <820000 820000 1200000>;
|
||||
};
|
||||
|
||||
opp@888000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <888000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000 880000 1200000>;
|
||||
opp-microvolt-speed1 = <820000 820000 1200000>;
|
||||
opp-microvolt-speed2 = <820000 820000 1200000>;
|
||||
};
|
||||
|
||||
opp@1080000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1080000000>;
|
||||
|
||||
opp-microvolt-speed0 = <940000 940000 1200000>;
|
||||
opp-microvolt-speed1 = <880000 880000 1200000>;
|
||||
opp-microvolt-speed2 = <880000 880000 1200000>;
|
||||
};
|
||||
|
||||
opp@1320000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1320000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1000000 1000000 1200000>;
|
||||
opp-microvolt-speed1 = <940000 940000 1200000>;
|
||||
opp-microvolt-speed2 = <940000 940000 1200000>;
|
||||
};
|
||||
|
||||
opp@1488000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1488000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1060000 1060000 1200000>;
|
||||
opp-microvolt-speed1 = <1000000 1000000 1200000>;
|
||||
opp-microvolt-speed2 = <1000000 1000000 1200000>;
|
||||
};
|
||||
|
||||
opp@1608000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1608000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1090000 1090000 1200000>;
|
||||
opp-microvolt-speed1 = <1030000 1030000 1200000>;
|
||||
opp-microvolt-speed2 = <1030000 1030000 1200000>;
|
||||
};
|
||||
|
||||
opp@1704000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1704000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1120000 1120000 1200000>;
|
||||
opp-microvolt-speed1 = <1060000 1060000 1200000>;
|
||||
opp-microvolt-speed2 = <1060000 1060000 1200000>;
|
||||
};
|
||||
|
||||
opp@1800000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1160000 1160000 1200000>;
|
||||
opp-microvolt-speed1 = <1100000 1100000 1200000>;
|
||||
opp-microvolt-speed2 = <1100000 1100000 1200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
|
@ -4,6 +4,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sun50i-h6.dtsi"
|
||||
#include "sun50i-h6-cpu-opp.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -257,6 +258,7 @@
|
|||
regulator-always-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1160000>;
|
||||
regulator-ramp-delay = <2500>;
|
||||
regulator-name = "vdd-cpu";
|
||||
};
|
||||
|
||||
|
|
@ -264,6 +266,7 @@
|
|||
regulator-enable-ramp-delay = <32000>;
|
||||
regulator-min-microvolt = <810000>;
|
||||
regulator-max-microvolt = <1080000>;
|
||||
regulator-ramp-delay = <2500>;
|
||||
regulator-name = "vdd-gpu";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -6,4 +6,69 @@
|
|||
/ {
|
||||
model = "OrangePi Lite2";
|
||||
compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
|
||||
|
||||
aliases {
|
||||
serial1 = &uart1; /* BT-UART */
|
||||
};
|
||||
|
||||
wifi_pwrseq: wifi_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rtc 1>;
|
||||
clock-names = "ext_clock";
|
||||
reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
|
||||
post-power-on-delay-ms = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <®_cldo2>;
|
||||
vqmmc-supply = <®_bldo3>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
|
||||
brcm: sdio-wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&r_pio>;
|
||||
interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
®_cldo2 {
|
||||
/*
|
||||
* This regulator is connected with CLDO3.
|
||||
* Before the kernel can support synchronized
|
||||
* enable of coupled regulators, keep them
|
||||
* both always on as a ugly hack.
|
||||
*/
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
®_cldo3 {
|
||||
/*
|
||||
* This regulator is connected with CLDO2.
|
||||
* See the comments for CLDO2.
|
||||
*/
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* There's the BT part of the AP6255 connected to that UART */
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm4345c5";
|
||||
clocks = <&rtc 1>;
|
||||
clock-names = "lpo";
|
||||
device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
|
||||
host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
|
||||
shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
|
||||
max-speed = <1500000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -106,6 +106,12 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
vcc-pc-supply = <®_bldo2>;
|
||||
vcc-pd-supply = <®_cldo1>;
|
||||
vcc-pg-supply = <®_aldo1>;
|
||||
};
|
||||
|
||||
&r_i2c {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -230,6 +236,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&r_pio {
|
||||
vcc-pm-supply = <®_bldo3>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&ext_osc32k>;
|
||||
};
|
||||
|
|
@ -241,7 +251,12 @@
|
|||
};
|
||||
|
||||
&usb2otg {
|
||||
dr_mode = "otg";
|
||||
/*
|
||||
* OrangePi Lite 2 and One Plus, where this DT is used, don't
|
||||
* have a controllable VBUS even though they do have an ID pin.
|
||||
* Using it as anything but a USB host is unsafe.
|
||||
*/
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sun50i-h6.dtsi"
|
||||
#include "sun50i-h6-cpu-opp.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -80,6 +81,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <®_dcdca>;
|
||||
};
|
||||
|
||||
&de {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ext_rgmii_pins>;
|
||||
|
|
@ -91,17 +108,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
ext_rgmii_phy: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&de {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <®_dcdcc>;
|
||||
status = "okay";
|
||||
|
|
@ -117,12 +123,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci3 {
|
||||
status = "okay";
|
||||
&mdio {
|
||||
ext_rgmii_phy: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
|
|
@ -238,7 +243,8 @@
|
|||
reg_dcdca: dcdca {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <810000>;
|
||||
regulator-max-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <1160000>;
|
||||
regulator-ramp-delay = <2500>;
|
||||
regulator-name = "vdd-cpu";
|
||||
};
|
||||
|
||||
|
|
@ -246,6 +252,7 @@
|
|||
regulator-enable-ramp-delay = <32000>;
|
||||
regulator-min-microvolt = <810000>;
|
||||
regulator-max-microvolt = <1080000>;
|
||||
regulator-ramp-delay = <2500>;
|
||||
regulator-name = "vdd-gpu";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sun50i-h6.dtsi"
|
||||
#include "sun50i-h6-cpu-opp.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -37,6 +38,17 @@
|
|||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_vdd_cpu_gpu: vdd-cpu-gpu {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd-cpu-gpu";
|
||||
regulator-min-microvolt = <1135000>;
|
||||
regulator-max-microvolt = <1135000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <®_vdd_cpu_gpu>;
|
||||
};
|
||||
|
||||
&de {
|
||||
|
|
@ -56,6 +68,7 @@
|
|||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <®_vdd_cpu_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@
|
|||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
|
|
@ -32,6 +35,9 @@
|
|||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
|
|
@ -39,6 +45,9 @@
|
|||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
|
|
@ -46,6 +55,9 @@
|
|||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -123,6 +135,7 @@
|
|||
clock-names = "bus",
|
||||
"mod";
|
||||
resets = <&display_clocks RST_MIXER0>;
|
||||
iommus = <&iommu 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -231,6 +244,16 @@
|
|||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
msgbox: mailbox@3003000 {
|
||||
compatible = "allwinner,sun50i-h6-msgbox",
|
||||
"allwinner,sun6i-a31-msgbox";
|
||||
reg = <0x03003000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_MSGBOX>;
|
||||
resets = <&ccu RST_BUS_MSGBOX>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
sid: efuse@3006000 {
|
||||
compatible = "allwinner,sun50i-h6-sid";
|
||||
reg = <0x03006000 0x400>;
|
||||
|
|
@ -240,6 +263,10 @@
|
|||
ths_calibration: thermal-sensor-calibration@14 {
|
||||
reg = <0x14 0x8>;
|
||||
};
|
||||
|
||||
cpu_speed_grade: cpu-speed-grade@1c {
|
||||
reg = <0x1c 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@30090a0 {
|
||||
|
|
@ -387,6 +414,15 @@
|
|||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
iommu: iommu@30f0000 {
|
||||
compatible = "allwinner,sun50i-h6-iommu";
|
||||
reg = <0x030f0000 0x10000>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_IOMMU>;
|
||||
resets = <&ccu RST_BUS_IOMMU>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
mmc0: mmc@4020000 {
|
||||
compatible = "allwinner,sun50i-h6-mmc",
|
||||
"allwinner,sun50i-a64-mmc";
|
||||
|
|
@ -946,6 +982,30 @@
|
|||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&ths 0>;
|
||||
|
||||
trips {
|
||||
cpu_alert: cpu-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu-thermal {
|
||||
|
|
|
|||
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