soc bcm: brcmstb: Add support for S2/S3/S5 suspend states (MIPS)
This commit adds support for the Broadcom STB S2/S3/S5 suspend states on MIPS based SoCs. This requires quite a lot of code in order to deal with the different HW blocks that need to be quiesced during suspend: - DDR PHY - DDR memory controller and arbiter - control processor The final steps of the suspend execute in cache and there is is a little bit of assembly code in order to shut down the DDR PHY PLL and then go into a wait loop until a wake-up even occurs. Conversely the resume part involves waiting for the DDR PHY PLL to come back up and resume executions where we left. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
Justin Chen
Florian Fainelli
Родитель
dedcf233ce
Коммит
0e9b114132
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@ -4,7 +4,7 @@ config BRCMSTB_PM
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bool "Support suspend/resume for STB platforms"
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default y
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depends on PM
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depends on ARCH_BRCMSTB
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depends on ARCH_BRCMSTB || BMIPS_GENERIC
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select ARM_CPU_SUSPEND if ARM
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endif # SOC_BRCMSTB
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@ -1,2 +1,3 @@
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obj-$(CONFIG_ARM) += s2-arm.o pm-arm.o
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AFLAGS_s2-arm.o := -march=armv7-a
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obj-$(CONFIG_BMIPS_GENERIC) += s2-mips.o s3-mips.o pm-mips.o
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@ -0,0 +1,461 @@
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/*
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* MIPS-specific support for Broadcom STB S2/S3/S5 power management
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*
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* Copyright (C) 2016-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/suspend.h>
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#include <asm/bmips.h>
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#include <asm/tlbflush.h>
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#include "pm.h"
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#define S2_NUM_PARAMS 6
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#define MAX_NUM_MEMC 3
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/* S3 constants */
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#define MAX_GP_REGS 16
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#define MAX_CP0_REGS 32
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#define NUM_MEMC_CLIENTS 128
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#define AON_CTRL_RAM_SIZE 128
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#define BRCMSTB_S3_MAGIC 0x5AFEB007
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#define CLEAR_RESET_MASK 0x01
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/* Index each CP0 register that needs to be saved */
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#define CONTEXT 0
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#define USER_LOCAL 1
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#define PGMK 2
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#define HWRENA 3
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#define COMPARE 4
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#define STATUS 5
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#define CONFIG 6
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#define MODE 7
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#define EDSP 8
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#define BOOT_VEC 9
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#define EBASE 10
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struct brcmstb_memc {
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void __iomem *ddr_phy_base;
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void __iomem *arb_base;
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};
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struct brcmstb_pm_control {
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void __iomem *aon_ctrl_base;
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void __iomem *aon_sram_base;
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void __iomem *timers_base;
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struct brcmstb_memc memcs[MAX_NUM_MEMC];
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int num_memc;
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};
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struct brcm_pm_s3_context {
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u32 cp0_regs[MAX_CP0_REGS];
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u32 memc0_rts[NUM_MEMC_CLIENTS];
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u32 sc_boot_vec;
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};
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struct brcmstb_mem_transfer;
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struct brcmstb_mem_transfer {
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struct brcmstb_mem_transfer *next;
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void *src;
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void *dst;
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dma_addr_t pa_src;
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dma_addr_t pa_dst;
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u32 len;
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u8 key;
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u8 mode;
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u8 src_remapped;
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u8 dst_remapped;
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u8 src_dst_remapped;
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};
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#define AON_SAVE_SRAM(base, idx, val) \
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__raw_writel(val, base + (idx << 2))
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/* Used for saving registers in asm */
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u32 gp_regs[MAX_GP_REGS];
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#define BSP_CLOCK_STOP 0x00
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#define PM_INITIATE 0x01
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static struct brcmstb_pm_control ctrl;
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static void brcm_pm_save_cp0_context(struct brcm_pm_s3_context *ctx)
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{
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/* Generic MIPS */
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ctx->cp0_regs[CONTEXT] = read_c0_context();
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ctx->cp0_regs[USER_LOCAL] = read_c0_userlocal();
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ctx->cp0_regs[PGMK] = read_c0_pagemask();
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ctx->cp0_regs[HWRENA] = read_c0_cache();
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ctx->cp0_regs[COMPARE] = read_c0_compare();
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ctx->cp0_regs[STATUS] = read_c0_status();
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/* Broadcom specific */
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ctx->cp0_regs[CONFIG] = read_c0_brcm_config();
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ctx->cp0_regs[MODE] = read_c0_brcm_mode();
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ctx->cp0_regs[EDSP] = read_c0_brcm_edsp();
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ctx->cp0_regs[BOOT_VEC] = read_c0_brcm_bootvec();
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ctx->cp0_regs[EBASE] = read_c0_ebase();
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ctx->sc_boot_vec = bmips_read_zscm_reg(0xa0);
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}
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static void brcm_pm_restore_cp0_context(struct brcm_pm_s3_context *ctx)
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{
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/* Restore cp0 state */
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bmips_write_zscm_reg(0xa0, ctx->sc_boot_vec);
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/* Generic MIPS */
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write_c0_context(ctx->cp0_regs[CONTEXT]);
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write_c0_userlocal(ctx->cp0_regs[USER_LOCAL]);
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write_c0_pagemask(ctx->cp0_regs[PGMK]);
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write_c0_cache(ctx->cp0_regs[HWRENA]);
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write_c0_compare(ctx->cp0_regs[COMPARE]);
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write_c0_status(ctx->cp0_regs[STATUS]);
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/* Broadcom specific */
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write_c0_brcm_config(ctx->cp0_regs[CONFIG]);
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write_c0_brcm_mode(ctx->cp0_regs[MODE]);
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write_c0_brcm_edsp(ctx->cp0_regs[EDSP]);
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write_c0_brcm_bootvec(ctx->cp0_regs[BOOT_VEC]);
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write_c0_ebase(ctx->cp0_regs[EBASE]);
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}
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static void brcmstb_pm_handshake(void)
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{
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void __iomem *base = ctrl.aon_ctrl_base;
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u32 tmp;
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/* BSP power handshake, v1 */
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tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
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tmp &= ~1UL;
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__raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS);
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(void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
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__raw_writel(0, base + AON_CTRL_PM_INITIATE);
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(void)__raw_readl(base + AON_CTRL_PM_INITIATE);
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__raw_writel(BSP_CLOCK_STOP | PM_INITIATE,
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base + AON_CTRL_PM_INITIATE);
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/*
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* HACK: BSP may have internal race on the CLOCK_STOP command.
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* Avoid touching the BSP for a few milliseconds.
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*/
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mdelay(3);
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}
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static void brcmstb_pm_s5(void)
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{
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void __iomem *base = ctrl.aon_ctrl_base;
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brcmstb_pm_handshake();
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/* Clear magic s3 warm-boot value */
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AON_SAVE_SRAM(ctrl.aon_sram_base, 0, 0);
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/* Set the countdown */
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__raw_writel(0x10, base + AON_CTRL_PM_CPU_WAIT_COUNT);
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(void)__raw_readl(base + AON_CTRL_PM_CPU_WAIT_COUNT);
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/* Prepare to S5 cold boot */
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__raw_writel(PM_COLD_CONFIG, base + AON_CTRL_PM_CTRL);
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(void)__raw_readl(base + AON_CTRL_PM_CTRL);
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__raw_writel((PM_COLD_CONFIG | PM_PWR_DOWN), base +
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AON_CTRL_PM_CTRL);
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(void)__raw_readl(base + AON_CTRL_PM_CTRL);
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__asm__ __volatile__(
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" wait\n"
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: : : "memory");
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}
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static int brcmstb_pm_s3(void)
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{
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struct brcm_pm_s3_context s3_context;
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void __iomem *memc_arb_base;
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unsigned long flags;
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u32 tmp;
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int i;
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/* Prepare for s3 */
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AON_SAVE_SRAM(ctrl.aon_sram_base, 0, BRCMSTB_S3_MAGIC);
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AON_SAVE_SRAM(ctrl.aon_sram_base, 1, (u32)&s3_reentry);
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AON_SAVE_SRAM(ctrl.aon_sram_base, 2, 0);
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/* Clear RESET_HISTORY */
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tmp = __raw_readl(ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
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tmp &= ~CLEAR_RESET_MASK;
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__raw_writel(tmp, ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
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local_irq_save(flags);
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/* Inhibit DDR_RSTb pulse for both MMCs*/
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for (i = 0; i < ctrl.num_memc; i++) {
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tmp = __raw_readl(ctrl.memcs[i].ddr_phy_base +
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DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
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tmp &= ~0x0f;
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__raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
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DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
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tmp |= (0x05 | BIT(5));
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__raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
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DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
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}
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/* Save CP0 context */
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brcm_pm_save_cp0_context(&s3_context);
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/* Save RTS(skip debug register) */
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memc_arb_base = ctrl.memcs[0].arb_base + 4;
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for (i = 0; i < NUM_MEMC_CLIENTS; i++) {
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s3_context.memc0_rts[i] = __raw_readl(memc_arb_base);
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memc_arb_base += 4;
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}
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/* Save I/O context */
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local_flush_tlb_all();
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_dma_cache_wback_inv(0, ~0);
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brcm_pm_do_s3(ctrl.aon_ctrl_base, current_cpu_data.dcache.linesz);
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/* CPU reconfiguration */
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local_flush_tlb_all();
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bmips_cpu_setup();
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cpumask_clear(&bmips_booted_mask);
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/* Restore RTS (skip debug register) */
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memc_arb_base = ctrl.memcs[0].arb_base + 4;
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for (i = 0; i < NUM_MEMC_CLIENTS; i++) {
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__raw_writel(s3_context.memc0_rts[i], memc_arb_base);
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memc_arb_base += 4;
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}
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/* restore CP0 context */
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brcm_pm_restore_cp0_context(&s3_context);
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local_irq_restore(flags);
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return 0;
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}
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static int brcmstb_pm_s2(void)
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{
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/*
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* We need to pass 6 arguments to an assembly function. Lets avoid the
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* stack and pass arguments in a explicit 4 byte array. The assembly
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* code assumes all arguments are 4 bytes and arguments are ordered
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* like so:
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*
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* 0: AON_CTRl base register
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* 1: DDR_PHY base register
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* 2: TIMERS base resgister
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* 3: I-Cache line size
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* 4: Restart vector address
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* 5: Restart vector size
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*/
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u32 s2_params[6];
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/* Prepare s2 parameters */
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s2_params[0] = (u32)ctrl.aon_ctrl_base;
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s2_params[1] = (u32)ctrl.memcs[0].ddr_phy_base;
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s2_params[2] = (u32)ctrl.timers_base;
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s2_params[3] = (u32)current_cpu_data.icache.linesz;
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s2_params[4] = (u32)BMIPS_WARM_RESTART_VEC;
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s2_params[5] = (u32)(bmips_smp_int_vec_end -
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bmips_smp_int_vec);
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/* Drop to standby */
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brcm_pm_do_s2(s2_params);
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return 0;
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}
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static int brcmstb_pm_standby(bool deep_standby)
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{
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brcmstb_pm_handshake();
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/* Send IRQs to BMIPS_WARM_RESTART_VEC */
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clear_c0_cause(CAUSEF_IV);
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irq_disable_hazard();
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set_c0_status(ST0_BEV);
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irq_disable_hazard();
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if (deep_standby)
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brcmstb_pm_s3();
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else
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brcmstb_pm_s2();
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/* Send IRQs to normal runtime vectors */
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clear_c0_status(ST0_BEV);
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irq_disable_hazard();
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set_c0_cause(CAUSEF_IV);
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irq_disable_hazard();
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return 0;
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}
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static int brcmstb_pm_enter(suspend_state_t state)
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{
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int ret = -EINVAL;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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ret = brcmstb_pm_standby(false);
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break;
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case PM_SUSPEND_MEM:
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ret = brcmstb_pm_standby(true);
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break;
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}
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return ret;
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}
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static int brcmstb_pm_valid(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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return true;
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case PM_SUSPEND_MEM:
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return true;
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default:
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return false;
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}
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}
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static const struct platform_suspend_ops brcmstb_pm_ops = {
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.enter = brcmstb_pm_enter,
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.valid = brcmstb_pm_valid,
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};
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static const struct of_device_id aon_ctrl_dt_ids[] = {
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{ .compatible = "brcm,brcmstb-aon-ctrl" },
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{ /* sentinel */ }
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};
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static const struct of_device_id ddr_phy_dt_ids[] = {
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{ .compatible = "brcm,brcmstb-ddr-phy" },
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{ /* sentinel */ }
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};
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static const struct of_device_id arb_dt_ids[] = {
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{ .compatible = "brcm,brcmstb-memc-arb" },
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{ /* sentinel */ }
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};
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static const struct of_device_id timers_ids[] = {
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{ .compatible = "brcm,brcmstb-timers" },
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{ /* sentinel */ }
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};
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static inline void __iomem *brcmstb_ioremap_node(struct device_node *dn,
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int index)
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{
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return of_io_request_and_map(dn, index, dn->full_name);
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}
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static void __iomem *brcmstb_ioremap_match(const struct of_device_id *matches,
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int index, const void **ofdata)
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{
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struct device_node *dn;
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const struct of_device_id *match;
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dn = of_find_matching_node_and_match(NULL, matches, &match);
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if (!dn)
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return ERR_PTR(-EINVAL);
|
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|
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if (ofdata)
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*ofdata = match->data;
|
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|
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return brcmstb_ioremap_node(dn, index);
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}
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|
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static int brcmstb_pm_init(void)
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{
|
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struct device_node *dn;
|
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void __iomem *base;
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int i;
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/* AON ctrl registers */
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base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL);
|
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if (IS_ERR(base)) {
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pr_err("error mapping AON_CTRL\n");
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goto aon_err;
|
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}
|
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ctrl.aon_ctrl_base = base;
|
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/* AON SRAM registers */
|
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base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL);
|
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if (IS_ERR(base)) {
|
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pr_err("error mapping AON_SRAM\n");
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goto sram_err;
|
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}
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ctrl.aon_sram_base = base;
|
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|
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ctrl.num_memc = 0;
|
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/* Map MEMC DDR PHY registers */
|
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for_each_matching_node(dn, ddr_phy_dt_ids) {
|
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i = ctrl.num_memc;
|
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if (i >= MAX_NUM_MEMC) {
|
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pr_warn("Too many MEMCs (max %d)\n", MAX_NUM_MEMC);
|
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break;
|
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}
|
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base = brcmstb_ioremap_node(dn, 0);
|
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if (IS_ERR(base))
|
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goto ddr_err;
|
||||
|
||||
ctrl.memcs[i].ddr_phy_base = base;
|
||||
ctrl.num_memc++;
|
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}
|
||||
|
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/* MEMC ARB registers */
|
||||
base = brcmstb_ioremap_match(arb_dt_ids, 0, NULL);
|
||||
if (IS_ERR(base)) {
|
||||
pr_err("error mapping MEMC ARB\n");
|
||||
goto ddr_err;
|
||||
}
|
||||
ctrl.memcs[0].arb_base = base;
|
||||
|
||||
/* Timer registers */
|
||||
base = brcmstb_ioremap_match(timers_ids, 0, NULL);
|
||||
if (IS_ERR(base)) {
|
||||
pr_err("error mapping timers\n");
|
||||
goto tmr_err;
|
||||
}
|
||||
ctrl.timers_base = base;
|
||||
|
||||
/* s3 cold boot aka s5 */
|
||||
pm_power_off = brcmstb_pm_s5;
|
||||
|
||||
suspend_set_ops(&brcmstb_pm_ops);
|
||||
|
||||
return 0;
|
||||
|
||||
tmr_err:
|
||||
iounmap(ctrl.memcs[0].arb_base);
|
||||
ddr_err:
|
||||
for (i = 0; i < ctrl.num_memc; i++)
|
||||
iounmap(ctrl.memcs[i].ddr_phy_base);
|
||||
|
||||
iounmap(ctrl.aon_sram_base);
|
||||
sram_err:
|
||||
iounmap(ctrl.aon_ctrl_base);
|
||||
aon_err:
|
||||
return PTR_ERR(base);
|
||||
}
|
||||
arch_initcall(brcmstb_pm_init);
|
||||
|
|
@ -70,9 +70,20 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifndef CONFIG_MIPS
|
||||
extern const unsigned long brcmstb_pm_do_s2_sz;
|
||||
extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base,
|
||||
void __iomem *ddr_phy_pll_status);
|
||||
#else
|
||||
/* s2 asm */
|
||||
extern asmlinkage int brcm_pm_do_s2(u32 *s2_params);
|
||||
|
||||
/* s3 asm */
|
||||
extern asmlinkage int brcm_pm_do_s3(void __iomem *aon_ctrl_base,
|
||||
int dcache_linesz);
|
||||
extern int s3_reentry;
|
||||
#endif /* CONFIG_MIPS */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __BRCMSTB_PM_H__ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/stackframe.h>
|
||||
|
||||
#include "pm.h"
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
.align 5
|
||||
|
||||
/*
|
||||
* a0: u32 params array
|
||||
*/
|
||||
LEAF(brcm_pm_do_s2)
|
||||
|
||||
subu sp, 64
|
||||
sw ra, 0(sp)
|
||||
sw s0, 4(sp)
|
||||
sw s1, 8(sp)
|
||||
sw s2, 12(sp)
|
||||
sw s3, 16(sp)
|
||||
sw s4, 20(sp)
|
||||
sw s5, 24(sp)
|
||||
sw s6, 28(sp)
|
||||
sw s7, 32(sp)
|
||||
|
||||
/*
|
||||
* Dereference the params array
|
||||
* s0: AON_CTRL base register
|
||||
* s1: DDR_PHY base register
|
||||
* s2: TIMERS base register
|
||||
* s3: I-Cache line size
|
||||
* s4: Restart vector address
|
||||
* s5: Restart vector size
|
||||
*/
|
||||
move t0, a0
|
||||
|
||||
lw s0, 0(t0)
|
||||
lw s1, 4(t0)
|
||||
lw s2, 8(t0)
|
||||
lw s3, 12(t0)
|
||||
lw s4, 16(t0)
|
||||
lw s5, 20(t0)
|
||||
|
||||
/* Lock this asm section into the I-cache */
|
||||
addiu t1, s3, -1
|
||||
not t1
|
||||
|
||||
la t0, brcm_pm_do_s2
|
||||
and t0, t1
|
||||
|
||||
la t2, asm_end
|
||||
and t2, t1
|
||||
|
||||
1: cache 0x1c, 0(t0)
|
||||
bne t0, t2, 1b
|
||||
addu t0, s3
|
||||
|
||||
/* Lock the interrupt vector into the I-cache */
|
||||
move t0, zero
|
||||
|
||||
2: move t1, s4
|
||||
cache 0x1c, 0(t1)
|
||||
addu t1, s3
|
||||
addu t0, s3
|
||||
ble t0, s5, 2b
|
||||
nop
|
||||
|
||||
sync
|
||||
|
||||
/* Power down request */
|
||||
li t0, PM_S2_COMMAND
|
||||
sw zero, AON_CTRL_PM_CTRL(s0)
|
||||
lw zero, AON_CTRL_PM_CTRL(s0)
|
||||
sw t0, AON_CTRL_PM_CTRL(s0)
|
||||
lw t0, AON_CTRL_PM_CTRL(s0)
|
||||
|
||||
/* Enable CP0 interrupt 2 and wait for interrupt */
|
||||
mfc0 t0, CP0_STATUS
|
||||
/* Save cp0 sr for restoring later */
|
||||
move s6, t0
|
||||
|
||||
li t1, ~(ST0_IM | ST0_IE)
|
||||
and t0, t1
|
||||
ori t0, STATUSF_IP2
|
||||
mtc0 t0, CP0_STATUS
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ori t0, ST0_IE
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
/* Wait for interrupt */
|
||||
wait
|
||||
nop
|
||||
|
||||
/* Wait for memc0 */
|
||||
1: lw t0, DDR40_PHY_CONTROL_REGS_0_PLL_STATUS(s1)
|
||||
andi t0, 1
|
||||
beqz t0, 1b
|
||||
nop
|
||||
|
||||
/* 1ms delay needed for stable recovery */
|
||||
/* Use TIMER1 to count 1 ms */
|
||||
li t0, RESET_TIMER
|
||||
sw t0, TIMER_TIMER1_CTRL(s2)
|
||||
lw t0, TIMER_TIMER1_CTRL(s2)
|
||||
|
||||
li t0, START_TIMER
|
||||
sw t0, TIMER_TIMER1_CTRL(s2)
|
||||
lw t0, TIMER_TIMER1_CTRL(s2)
|
||||
|
||||
/* Prepare delay */
|
||||
li t0, TIMER_MASK
|
||||
lw t1, TIMER_TIMER1_STAT(s2)
|
||||
and t1, t0
|
||||
/* 1ms delay */
|
||||
addi t1, 27000
|
||||
|
||||
/* Wait for the timer value to exceed t1 */
|
||||
1: lw t0, TIMER_TIMER1_STAT(s2)
|
||||
sgtu t2, t1, t0
|
||||
bnez t2, 1b
|
||||
nop
|
||||
|
||||
/* Power back up */
|
||||
li t1, 1
|
||||
sw t1, AON_CTRL_HOST_MISC_CMDS(s0)
|
||||
lw t1, AON_CTRL_HOST_MISC_CMDS(s0)
|
||||
|
||||
sw zero, AON_CTRL_PM_CTRL(s0)
|
||||
lw zero, AON_CTRL_PM_CTRL(s0)
|
||||
|
||||
/* Unlock I-cache */
|
||||
addiu t1, s3, -1
|
||||
not t1
|
||||
|
||||
la t0, brcm_pm_do_s2
|
||||
and t0, t1
|
||||
|
||||
la t2, asm_end
|
||||
and t2, t1
|
||||
|
||||
1: cache 0x00, 0(t0)
|
||||
bne t0, t2, 1b
|
||||
addu t0, s3
|
||||
|
||||
/* Unlock interrupt vector */
|
||||
move t0, zero
|
||||
|
||||
2: move t1, s4
|
||||
cache 0x00, 0(t1)
|
||||
addu t1, s3
|
||||
addu t0, s3
|
||||
ble t0, s5, 2b
|
||||
nop
|
||||
|
||||
/* Restore cp0 sr */
|
||||
sync
|
||||
nop
|
||||
mtc0 s6, CP0_STATUS
|
||||
nop
|
||||
|
||||
/* Set return value to success */
|
||||
li v0, 0
|
||||
|
||||
/* Return to caller */
|
||||
lw s7, 32(sp)
|
||||
lw s6, 28(sp)
|
||||
lw s5, 24(sp)
|
||||
lw s4, 20(sp)
|
||||
lw s3, 16(sp)
|
||||
lw s2, 12(sp)
|
||||
lw s1, 8(sp)
|
||||
lw s0, 4(sp)
|
||||
lw ra, 0(sp)
|
||||
addiu sp, 64
|
||||
|
||||
jr ra
|
||||
nop
|
||||
END(brcm_pm_do_s2)
|
||||
|
||||
.globl asm_end
|
||||
asm_end:
|
||||
nop
|
||||
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/bmips.h>
|
||||
|
||||
#include "pm.h"
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
.align 5
|
||||
.global s3_reentry
|
||||
|
||||
/*
|
||||
* a0: AON_CTRL base register
|
||||
* a1: D-Cache line size
|
||||
*/
|
||||
LEAF(brcm_pm_do_s3)
|
||||
|
||||
/* Get the address of s3_context */
|
||||
la t0, gp_regs
|
||||
sw ra, 0(t0)
|
||||
sw s0, 4(t0)
|
||||
sw s1, 8(t0)
|
||||
sw s2, 12(t0)
|
||||
sw s3, 16(t0)
|
||||
sw s4, 20(t0)
|
||||
sw s5, 24(t0)
|
||||
sw s6, 28(t0)
|
||||
sw s7, 32(t0)
|
||||
sw gp, 36(t0)
|
||||
sw sp, 40(t0)
|
||||
sw fp, 44(t0)
|
||||
|
||||
/* Save CP0 Status */
|
||||
mfc0 t1, CP0_STATUS
|
||||
sw t1, 48(t0)
|
||||
|
||||
/* Write-back gp registers - cache will be gone */
|
||||
addiu t1, a1, -1
|
||||
not t1
|
||||
and t0, t1
|
||||
|
||||
/* Flush at least 64 bytes */
|
||||
addiu t2, t0, 64
|
||||
and t2, t1
|
||||
|
||||
1: cache 0x17, 0(t0)
|
||||
bne t0, t2, 1b
|
||||
addu t0, a1
|
||||
|
||||
/* Drop to deep standby */
|
||||
li t1, PM_WARM_CONFIG
|
||||
sw zero, AON_CTRL_PM_CTRL(a0)
|
||||
lw zero, AON_CTRL_PM_CTRL(a0)
|
||||
sw t1, AON_CTRL_PM_CTRL(a0)
|
||||
lw t1, AON_CTRL_PM_CTRL(a0)
|
||||
|
||||
li t1, (PM_WARM_CONFIG | PM_PWR_DOWN)
|
||||
sw t1, AON_CTRL_PM_CTRL(a0)
|
||||
lw t1, AON_CTRL_PM_CTRL(a0)
|
||||
|
||||
/* Enable CP0 interrupt 2 and wait for interrupt */
|
||||
mfc0 t0, CP0_STATUS
|
||||
|
||||
li t1, ~(ST0_IM | ST0_IE)
|
||||
and t0, t1
|
||||
ori t0, STATUSF_IP2
|
||||
mtc0 t0, CP0_STATUS
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ori t0, ST0_IE
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
/* Wait for interrupt */
|
||||
wait
|
||||
nop
|
||||
|
||||
s3_reentry:
|
||||
|
||||
/* Clear call/return stack */
|
||||
li t0, (0x06 << 16)
|
||||
mtc0 t0, $22, 2
|
||||
ssnop
|
||||
ssnop
|
||||
ssnop
|
||||
|
||||
/* Clear jump target buffer */
|
||||
li t0, (0x04 << 16)
|
||||
mtc0 t0, $22, 2
|
||||
ssnop
|
||||
ssnop
|
||||
ssnop
|
||||
|
||||
sync
|
||||
nop
|
||||
|
||||
/* Setup mmu defaults */
|
||||
mtc0 zero, CP0_WIRED
|
||||
mtc0 zero, CP0_ENTRYHI
|
||||
li k0, PM_DEFAULT_MASK
|
||||
mtc0 k0, CP0_PAGEMASK
|
||||
|
||||
li sp, BMIPS_WARM_RESTART_VEC
|
||||
la k0, plat_wired_tlb_setup
|
||||
jalr k0
|
||||
nop
|
||||
|
||||
/* Restore general purpose registers */
|
||||
la t0, gp_regs
|
||||
lw fp, 44(t0)
|
||||
lw sp, 40(t0)
|
||||
lw gp, 36(t0)
|
||||
lw s7, 32(t0)
|
||||
lw s6, 28(t0)
|
||||
lw s5, 24(t0)
|
||||
lw s4, 20(t0)
|
||||
lw s3, 16(t0)
|
||||
lw s2, 12(t0)
|
||||
lw s1, 8(t0)
|
||||
lw s0, 4(t0)
|
||||
lw ra, 0(t0)
|
||||
|
||||
/* Restore CP0 status */
|
||||
lw t1, 48(t0)
|
||||
mtc0 t1, CP0_STATUS
|
||||
|
||||
/* Return to caller */
|
||||
li v0, 0
|
||||
jr ra
|
||||
nop
|
||||
|
||||
END(brcm_pm_do_s3)
|
||||
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