Documentation/acpi/einj: Correct and streamline text
Streamline and simplify formulations, improve formatting and extend the injection example in the error injection write up for users which we carry in Documentation/. Add a paragraph about checking for EINJ support and expand the ACPI5.0 memory errors section, as requested by Tony. Acked-by: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1422553845-30717-1-git-send-email-bp@alien8.de Signed-off-by: Borislav Petkov <bp@suse.de>
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APEI Error INJection
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~~~~~~~~~~~~~~~~~~~~
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EINJ provides a hardware error injection mechanism
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It is very useful for debugging and testing of other APEI and RAS features.
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EINJ provides a hardware error injection mechanism. It is very useful
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for debugging and testing APEI and RAS features in general.
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To use EINJ, make sure the following are enabled in your kernel
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You need to check whether your BIOS supports EINJ first. For that, look
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for early boot messages similar to this one:
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ACPI: EINJ 0x000000007370A000 000150 (v01 INTEL 00000001 INTL 00000001)
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which shows that the BIOS is exposing an EINJ table - it is the
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mechanism through which the injection is done.
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Alternatively, look in /sys/firmware/acpi/tables for an "EINJ" file,
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which is a different representation of the same thing.
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It doesn't necessarily mean that EINJ is not supported if those above
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don't exist: before you give up, go into BIOS setup to see if the BIOS
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has an option to enable error injection. Look for something called WHEA
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or similar. Often, you need to enable an ACPI5 support option prior, in
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order to see the APEI,EINJ,... functionality supported and exposed by
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the BIOS menu.
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To use EINJ, make sure the following are options enabled in your kernel
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configuration:
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CONFIG_DEBUG_FS
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CONFIG_ACPI_APEI
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CONFIG_ACPI_APEI_EINJ
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The user interface of EINJ is debug file system, under the
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directory apei/einj. The following files are provided.
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The EINJ user interface is in <debugfs mount point>/apei/einj.
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The following files belong to it:
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- available_error_type
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Reading this file returns the error injection capability of the
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platform, that is, which error types are supported. The error type
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definition is as follow, the left field is the error type value, the
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right field is error description.
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This file shows which error types are supported:
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Error Type Value Error Description
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================ =================
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0x00000001 Processor Correctable
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0x00000002 Processor Uncorrectable non-fatal
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0x00000004 Processor Uncorrectable fatal
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@ -33,97 +52,126 @@ directory apei/einj. The following files are provided.
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0x00000400 Platform Uncorrectable non-fatal
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0x00000800 Platform Uncorrectable fatal
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The format of file contents are as above, except there are only the
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available error type lines.
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The format of the file contents are as above, except present are only
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the available error types.
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- error_type
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This file is used to set the error type value. The error type value
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is defined in "available_error_type" description.
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Set the value of the error type being injected. Possible error types
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are defined in the file available_error_type above.
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- error_inject
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Write any integer to this file to trigger the error
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injection. Before this, please specify all necessary error
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parameters.
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Write any integer to this file to trigger the error injection. Make
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sure you have specified all necessary error parameters, i.e. this
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write should be the last step when injecting errors.
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- flags
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Present for kernel version 3.13 and above. Used to specify which
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of param{1..4} are valid and should be used by BIOS during injection.
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Value is a bitmask as specified in ACPI5.0 spec for the
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Present for kernel versions 3.13 and above. Used to specify which
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of param{1..4} are valid and should be used by the firmware during
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injection. Value is a bitmask as specified in ACPI5.0 spec for the
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SET_ERROR_TYPE_WITH_ADDRESS data structure:
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Bit 0 - Processor APIC field valid (see param3 below)
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Bit 1 - Memory address and mask valid (param1 and param2)
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Bit 2 - PCIe (seg,bus,dev,fn) valid (param4 below)
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If set to zero, legacy behaviour is used where the type of injection
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specifies just one bit set, and param1 is multiplexed.
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Bit 0 - Processor APIC field valid (see param3 below).
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Bit 1 - Memory address and mask valid (param1 and param2).
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Bit 2 - PCIe (seg,bus,dev,fn) valid (see param4 below).
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If set to zero, legacy behavior is mimicked where the type of
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injection specifies just one bit set, and param1 is multiplexed.
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- param1
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This file is used to set the first error parameter value. Effect of
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parameter depends on error_type specified. For example, if error
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type is memory related type, the param1 should be a valid physical
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memory address. [Unless "flag" is set - see above]
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This file is used to set the first error parameter value. Its effect
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depends on the error type specified in error_type. For example, if
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error type is memory related type, the param1 should be a valid
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physical memory address. [Unless "flag" is set - see above]
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- param2
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This file is used to set the second error parameter value. Effect of
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parameter depends on error_type specified. For example, if error
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type is memory related type, the param2 should be a physical memory
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address mask. Linux requires page or narrower granularity, say,
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0xfffffffffffff000.
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Same use as param1 above. For example, if error type is of memory
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related type, then param2 should be a physical memory address mask.
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Linux requires page or narrower granularity, say, 0xfffffffffffff000.
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- param3
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Used when the 0x1 bit is set in "flag" to specify the APIC id
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Used when the 0x1 bit is set in "flags" to specify the APIC id
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- param4
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Used when the 0x4 bit is set in "flag" to specify target PCIe device
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Used when the 0x4 bit is set in "flags" to specify target PCIe device
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- notrigger
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The EINJ mechanism is a two step process. First inject the error, then
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perform some actions to trigger it. Setting "notrigger" to 1 skips the
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trigger phase, which *may* allow the user to cause the error in some other
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context by a simple access to the cpu, memory location, or device that is
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the target of the error injection. Whether this actually works depends
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on what operations the BIOS actually includes in the trigger phase.
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BIOS versions based in the ACPI 4.0 specification have limited options
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to control where the errors are injected. Your BIOS may support an
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extension (enabled with the param_extension=1 module parameter, or
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boot command line einj.param_extension=1). This allows the address
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and mask for memory injections to be specified by the param1 and
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param2 files in apei/einj.
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The error injection mechanism is a two-step process. First inject the
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error, then perform some actions to trigger it. Setting "notrigger"
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to 1 skips the trigger phase, which *may* allow the user to cause the
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error in some other context by a simple access to the CPU, memory
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location, or device that is the target of the error injection. Whether
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this actually works depends on what operations the BIOS actually
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includes in the trigger phase.
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BIOS versions using the ACPI 5.0 specification have more control over
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the target of the injection. For processor related errors (type 0x1,
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0x2 and 0x4) the APICID of the target should be provided using the
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param1 file in apei/einj. For memory errors (type 0x8, 0x10 and 0x20)
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the address is set using param1 with a mask in param2 (0x0 is equivalent
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to all ones). For PCI express errors (type 0x40, 0x80 and 0x100) the
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segment, bus, device and function are specified using param1:
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BIOS versions based on the ACPI 4.0 specification have limited options
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in controlling where the errors are injected. Your BIOS may support an
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extension (enabled with the param_extension=1 module parameter, or boot
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command line einj.param_extension=1). This allows the address and mask
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for memory injections to be specified by the param1 and param2 files in
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apei/einj.
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BIOS versions based on the ACPI 5.0 specification have more control over
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the target of the injection. For processor-related errors (type 0x1, 0x2
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and 0x4), you can set flags to 0x3 (param3 for bit 0, and param1 and
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param2 for bit 1) so that you have more information added to the error
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signature being injected. The actual data passed is this:
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memory_address = param1;
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memory_address_range = param2;
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apicid = param3;
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pcie_sbdf = param4;
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For memory errors (type 0x8, 0x10 and 0x20) the address is set using
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param1 with a mask in param2 (0x0 is equivalent to all ones). For PCI
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express errors (type 0x40, 0x80 and 0x100) the segment, bus, device and
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function are specified using param1:
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31 24 23 16 15 11 10 8 7 0
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+-------------------------------------------------+
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| segment | bus | device | function | reserved |
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+-------------------------------------------------+
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An ACPI 5.0 BIOS may also allow vendor specific errors to be injected.
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Anyway, you get the idea, if there's doubt just take a look at the code
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in drivers/acpi/apei/einj.c.
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An ACPI 5.0 BIOS may also allow vendor-specific errors to be injected.
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In this case a file named vendor will contain identifying information
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from the BIOS that hopefully will allow an application wishing to use
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the vendor specific extension to tell that they are running on a BIOS
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the vendor-specific extension to tell that they are running on a BIOS
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that supports it. All vendor extensions have the 0x80000000 bit set in
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error_type. A file vendor_flags controls the interpretation of param1
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and param2 (1 = PROCESSOR, 2 = MEMORY, 4 = PCI). See your BIOS vendor
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documentation for details (and expect changes to this API if vendors
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creativity in using this feature expands beyond our expectations).
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Example:
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An error injection example:
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# cd /sys/kernel/debug/apei/einj
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# cat available_error_type # See which errors can be injected
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0x00000002 Processor Uncorrectable non-fatal
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0x00000008 Memory Correctable
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0x00000010 Memory Uncorrectable non-fatal
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# echo 0x12345000 > param1 # Set memory address for injection
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# echo 0xfffffffffffff000 > param2 # Mask - anywhere in this page
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# echo $((-1 << 12)) > param2 # Mask 0xfffffffffffff000 - anywhere in this page
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# echo 0x8 > error_type # Choose correctable memory error
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# echo 1 > error_inject # Inject now
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You should see something like this in dmesg:
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[22715.830801] EDAC sbridge MC3: HANDLING MCE MEMORY ERROR
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[22715.834759] EDAC sbridge MC3: CPU 0: Machine Check Event: 0 Bank 7: 8c00004000010090
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[22715.834759] EDAC sbridge MC3: TSC 0
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[22715.834759] EDAC sbridge MC3: ADDR 12345000 EDAC sbridge MC3: MISC 144780c86
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[22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0
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[22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0)
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For more information about EINJ, please refer to ACPI specification
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version 4.0, section 17.5 and ACPI 5.0, section 18.6.
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