powerpc: Remove power3 from comments
There are still a few occurences where it remains, because it helps to explain something that persists. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -461,8 +461,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
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/*
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* Routine to copy a whole page of data, optimized for POWER4.
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* On POWER4 it is more than 50% faster than the simple loop
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* above (following the .Ldst_aligned label) but it runs slightly
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* slower on POWER3.
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* above (following the .Ldst_aligned label).
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*/
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.Lcopy_page_4K:
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std r31,-32(1)
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@ -2,7 +2,7 @@
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* This file contains the routines for handling the MMU on those
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* PowerPC implementations where the MMU substantially follows the
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* architecture specification. This includes the 6xx, 7xx, 7xxx,
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* 8260, and POWER3 implementations but excludes the 8xx and 4xx.
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* and 8260 implementations but excludes the 8xx and 4xx.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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@ -2,7 +2,7 @@
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* This file contains the routines for handling the MMU on those
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* PowerPC implementations where the MMU substantially follows the
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* architecture specification. This includes the 6xx, 7xx, 7xxx,
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* 8260, and POWER3 implementations but excludes the 8xx and 4xx.
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* and 8260 implementations but excludes the 8xx and 4xx.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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@ -61,7 +61,7 @@ choice
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help
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There are two families of 64 bit PowerPC chips supported.
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The most common ones are the desktop and server CPUs
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(POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...)
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(POWER4, POWER5, 970, POWER5+, POWER6, POWER7, POWER8 ...)
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The other are the "embedded" processors compliant with the
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"Book 3E" variant of the architecture
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