irqchip: mmp: support irqchip
Support IRQCHIP & CONFIG_MULTI_IRQ_HANDLER in irq-mmp driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: Daniel Drake <dsd@laptop.org>
This commit is contained in:
Haojian Zhuang
Родитель
c052d13c08
Коммит
0f374561b5
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@ -557,6 +557,7 @@ config ARCH_MMP
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select GENERIC_CLOCKEVENTS
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select GPIO_PXA
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select NEED_MACH_GPIO_H
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select PINCTRL
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select PLAT_PXA
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@ -1,26 +0,0 @@
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/*
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* linux/arch/arm/mach-mmp/include/mach/entry-macro.S
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/irq.h>
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#include <mach/regs-icu.h>
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.macro get_irqnr_preamble, base, tmp
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mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
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and \tmp, \tmp, #0xff00
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cmp \tmp, #0x5800
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ldr \base, =mmp_icu_base
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ldr \base, [\base, #0]
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addne \base, \base, #0x10c @ PJ1 AP INT SEL register
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addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \tmp, [\base, #0]
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and \irqnr, \tmp, #0x3f
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tst \tmp, #(1 << 6)
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.endm
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@ -9,17 +9,13 @@
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* publishhed by the Free Software Foundation.
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*/
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <mach/irqs.h>
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#include "common.h"
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extern void __init mmp_dt_irq_init(void);
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extern void __init mmp_dt_init_timer(void);
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static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
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@ -64,7 +60,6 @@ static const char *mmp_dt_board_compat[] __initdata = {
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DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
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.map_io = mmp_map_io,
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.init_irq = mmp_dt_irq_init,
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.init_time = mmp_dt_init_timer,
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.init_machine = pxa168_dt_init,
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.dt_compat = mmp_dt_board_compat,
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@ -72,7 +67,6 @@ MACHINE_END
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DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
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.map_io = mmp_map_io,
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.init_irq = mmp_dt_irq_init,
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.init_time = mmp_dt_init_timer,
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.init_machine = pxa910_dt_init,
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.dt_compat = mmp_dt_board_compat,
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@ -10,18 +10,13 @@
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <mach/irqs.h>
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#include <mach/regs-apbc.h>
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#include "common.h"
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extern void __init mmp_dt_irq_init(void);
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extern void __init mmp_dt_init_timer(void);
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static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
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@ -49,7 +44,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
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DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
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.map_io = mmp_map_io,
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.init_irq = mmp_dt_irq_init,
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.init_time = mmp_dt_init_timer,
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.init_machine = mmp2_dt_init,
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.dt_compat = mmp2_dt_board_compat,
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@ -21,6 +21,9 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <mach/irqs.h>
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#ifdef CONFIG_CPU_MMP2
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@ -30,8 +33,17 @@
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#include <mach/pm-pxa910.h>
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#endif
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#include "irqchip.h"
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#define MAX_ICU_NR 16
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#define PJ1_INT_SEL 0x10c
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#define PJ4_INT_SEL 0x104
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/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
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#define SEL_INT_PENDING (1 << 6)
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#define SEL_INT_NUM_MASK 0x3f
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struct icu_chip_data {
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int nr_irqs;
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unsigned int virq_base;
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@ -52,7 +64,7 @@ struct mmp_intc_conf {
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unsigned int conf_mask;
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};
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void __iomem *mmp_icu_base;
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static void __iomem *mmp_icu_base;
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static struct icu_chip_data icu_data[MAX_ICU_NR];
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static int max_icu_nr;
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@ -191,6 +203,32 @@ static struct mmp_intc_conf mmp2_conf = {
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.conf_mask = 0x7f,
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};
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static asmlinkage void __exception_irq_entry
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mmp_handle_irq(struct pt_regs *regs)
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{
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int irq, hwirq;
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hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
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if (!(hwirq & SEL_INT_PENDING))
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return;
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hwirq &= SEL_INT_NUM_MASK;
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irq = irq_find_mapping(icu_data[0].domain, hwirq);
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handle_IRQ(irq, regs);
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}
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static asmlinkage void __exception_irq_entry
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mmp2_handle_irq(struct pt_regs *regs)
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{
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int irq, hwirq;
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hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
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if (!(hwirq & SEL_INT_PENDING))
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return;
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hwirq &= SEL_INT_NUM_MASK;
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irq = irq_find_mapping(icu_data[0].domain, hwirq);
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handle_IRQ(irq, regs);
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}
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/* MMP (ARMv5) */
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void __init icu_init_irq(void)
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{
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@ -212,6 +250,7 @@ void __init icu_init_irq(void)
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set_irq_flags(irq, IRQF_VALID);
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}
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irq_set_default_host(icu_data[0].domain);
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set_handle_irq(mmp_handle_irq);
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#ifdef CONFIG_CPU_PXA910
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icu_irq_chip.irq_set_wake = pxa910_set_wake;
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#endif
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@ -318,144 +357,155 @@ void __init mmp2_init_icu(void)
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set_irq_flags(irq, IRQF_VALID);
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}
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irq_set_default_host(icu_data[0].domain);
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set_handle_irq(mmp2_handle_irq);
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#ifdef CONFIG_CPU_MMP2
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icu_irq_chip.irq_set_wake = mmp2_set_wake;
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#endif
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}
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#ifdef CONFIG_OF
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static const struct of_device_id intc_ids[] __initconst = {
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{ .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
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{ .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
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{}
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};
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static const struct of_device_id mmp_mux_irq_match[] __initconst = {
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{ .compatible = "mrvl,mmp2-mux-intc" },
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{}
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};
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int __init mmp2_mux_init(struct device_node *parent)
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static int __init mmp_init_bases(struct device_node *node)
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{
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struct device_node *node;
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const struct of_device_id *of_id;
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struct resource res;
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int i, irq_base, ret, irq;
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u32 nr_irqs, mfp_irq;
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node = parent;
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max_icu_nr = 1;
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for (i = 1; i < MAX_ICU_NR; i++) {
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node = of_find_matching_node(node, mmp_mux_irq_match);
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if (!node)
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break;
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of_id = of_match_node(&mmp_mux_irq_match[0], node);
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ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
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&nr_irqs);
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if (ret) {
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pr_err("Not found mrvl,intc-nr-irqs property\n");
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ret = -EINVAL;
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goto err;
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}
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ret = of_address_to_resource(node, 0, &res);
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if (ret < 0) {
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pr_err("Not found reg property\n");
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ret = -EINVAL;
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goto err;
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}
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icu_data[i].reg_status = mmp_icu_base + res.start;
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ret = of_address_to_resource(node, 1, &res);
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if (ret < 0) {
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pr_err("Not found reg property\n");
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ret = -EINVAL;
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goto err;
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}
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icu_data[i].reg_mask = mmp_icu_base + res.start;
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icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
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if (!icu_data[i].cascade_irq) {
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ret = -EINVAL;
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goto err;
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}
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irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
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if (irq_base < 0) {
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pr_err("Failed to allocate IRQ numbers for mux intc\n");
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ret = irq_base;
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goto err;
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}
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if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
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&mfp_irq)) {
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icu_data[i].clr_mfp_irq_base = irq_base;
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icu_data[i].clr_mfp_hwirq = mfp_irq;
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}
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irq_set_chained_handler(icu_data[i].cascade_irq,
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icu_mux_irq_demux);
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icu_data[i].nr_irqs = nr_irqs;
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icu_data[i].virq_base = irq_base;
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icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
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irq_base, 0,
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&mmp_irq_domain_ops,
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&icu_data[i]);
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for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
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icu_mask_irq(irq_get_irq_data(irq));
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}
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max_icu_nr = i;
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return 0;
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err:
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of_node_put(node);
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max_icu_nr = i;
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return ret;
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}
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void __init mmp_dt_irq_init(void)
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{
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struct device_node *node;
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const struct of_device_id *of_id;
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struct mmp_intc_conf *conf;
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int nr_irqs, irq_base, ret, irq;
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node = of_find_matching_node(NULL, intc_ids);
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if (!node) {
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pr_err("Failed to find interrupt controller in arch-mmp\n");
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return;
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}
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of_id = of_match_node(intc_ids, node);
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conf = of_id->data;
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int ret, nr_irqs, irq, i = 0;
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ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
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if (ret) {
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pr_err("Not found mrvl,intc-nr-irqs property\n");
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return;
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return ret;
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}
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mmp_icu_base = of_iomap(node, 0);
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if (!mmp_icu_base) {
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pr_err("Failed to get interrupt controller register\n");
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return;
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return -ENOMEM;
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}
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irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
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if (irq_base < 0) {
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pr_err("Failed to allocate IRQ numbers\n");
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goto err;
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} else if (irq_base != NR_IRQS_LEGACY) {
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pr_err("ICU's irqbase should be started from 0\n");
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goto err;
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}
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icu_data[0].conf_enable = conf->conf_enable;
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icu_data[0].conf_disable = conf->conf_disable;
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icu_data[0].conf_mask = conf->conf_mask;
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icu_data[0].nr_irqs = nr_irqs;
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icu_data[0].virq_base = 0;
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icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
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icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
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&mmp_irq_domain_ops,
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&icu_data[0]);
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irq_set_default_host(icu_data[0].domain);
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for (irq = 0; irq < nr_irqs; irq++)
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icu_mask_irq(irq_get_irq_data(irq));
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mmp2_mux_init(node);
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return;
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for (irq = 0; irq < nr_irqs; irq++) {
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ret = irq_create_mapping(icu_data[0].domain, irq);
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if (!ret) {
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pr_err("Failed to mapping hwirq\n");
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goto err;
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}
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if (!irq)
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icu_data[0].virq_base = ret;
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}
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icu_data[0].nr_irqs = nr_irqs;
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return 0;
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err:
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if (icu_data[0].virq_base) {
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for (i = 0; i < irq; i++)
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irq_dispose_mapping(icu_data[0].virq_base + i);
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}
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irq_domain_remove(icu_data[0].domain);
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iounmap(mmp_icu_base);
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return -EINVAL;
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}
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static int __init mmp_of_init(struct device_node *node,
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struct device_node *parent)
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{
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int ret;
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ret = mmp_init_bases(node);
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if (ret < 0)
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return ret;
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icu_data[0].conf_enable = mmp_conf.conf_enable;
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icu_data[0].conf_disable = mmp_conf.conf_disable;
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icu_data[0].conf_mask = mmp_conf.conf_mask;
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irq_set_default_host(icu_data[0].domain);
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set_handle_irq(mmp_handle_irq);
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max_icu_nr = 1;
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return 0;
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}
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IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
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static int __init mmp2_of_init(struct device_node *node,
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struct device_node *parent)
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{
|
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int ret;
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|
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ret = mmp_init_bases(node);
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if (ret < 0)
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return ret;
|
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|
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icu_data[0].conf_enable = mmp2_conf.conf_enable;
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icu_data[0].conf_disable = mmp2_conf.conf_disable;
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icu_data[0].conf_mask = mmp2_conf.conf_mask;
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irq_set_default_host(icu_data[0].domain);
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set_handle_irq(mmp2_handle_irq);
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max_icu_nr = 1;
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return 0;
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}
|
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IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
|
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|
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static int __init mmp2_mux_of_init(struct device_node *node,
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struct device_node *parent)
|
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{
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struct resource res;
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int i, ret, irq, j = 0;
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u32 nr_irqs, mfp_irq;
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|
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if (!parent)
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return -ENODEV;
|
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|
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i = max_icu_nr;
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ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
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&nr_irqs);
|
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if (ret) {
|
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pr_err("Not found mrvl,intc-nr-irqs property\n");
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return -EINVAL;
|
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}
|
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ret = of_address_to_resource(node, 0, &res);
|
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if (ret < 0) {
|
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pr_err("Not found reg property\n");
|
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return -EINVAL;
|
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}
|
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icu_data[i].reg_status = mmp_icu_base + res.start;
|
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ret = of_address_to_resource(node, 1, &res);
|
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if (ret < 0) {
|
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pr_err("Not found reg property\n");
|
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return -EINVAL;
|
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}
|
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icu_data[i].reg_mask = mmp_icu_base + res.start;
|
||||
icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
|
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if (!icu_data[i].cascade_irq)
|
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return -EINVAL;
|
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|
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icu_data[i].virq_base = 0;
|
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icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
|
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&mmp_irq_domain_ops,
|
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&icu_data[i]);
|
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for (irq = 0; irq < nr_irqs; irq++) {
|
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ret = irq_create_mapping(icu_data[i].domain, irq);
|
||||
if (!ret) {
|
||||
pr_err("Failed to mapping hwirq\n");
|
||||
goto err;
|
||||
}
|
||||
if (!irq)
|
||||
icu_data[i].virq_base = ret;
|
||||
}
|
||||
icu_data[i].nr_irqs = nr_irqs;
|
||||
if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
|
||||
&mfp_irq)) {
|
||||
icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
|
||||
icu_data[i].clr_mfp_hwirq = mfp_irq;
|
||||
}
|
||||
irq_set_chained_handler(icu_data[i].cascade_irq,
|
||||
icu_mux_irq_demux);
|
||||
max_icu_nr++;
|
||||
return 0;
|
||||
err:
|
||||
if (icu_data[i].virq_base) {
|
||||
for (j = 0; j < irq; j++)
|
||||
irq_dispose_mapping(icu_data[i].virq_base + j);
|
||||
}
|
||||
irq_domain_remove(icu_data[i].domain);
|
||||
return -EINVAL;
|
||||
}
|
||||
IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
|
||||
#endif
|
||||
|
|
|
|||
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