Two small fixes for the Zynq clock controller introduced in 3.11-rc1 and
another Exynos clock patch which fixes a regression that prevents the video pipeline from functioning on that platform. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJSCma3AAoJEDqPOy9afJhJI/QP/R5kIvB3osg7ZGXYXzHtC4nu EamZXz77Wg/fvpktaLP6C5eDjJgYKgUV2qwLvjurxRjpeJ4GmLlf0ieB8XknI8XQ 8BFjIk4ugvfqjWJ3VxO5Gcc1VdTAgpyZHVUbrmRMmAa/lWDO0BUFDdmyIguY7DoN ydrWKBESnT/4tQ2e+a0i+/mzBqaLOrc5hzL2g76TUHDNO0XlFQpVIO4buI9+dlpb maH9Be+Mg7q6JbTg6RdetZuJ7IowaYSOL5fDmGJPBuzbclpZ4fmDjpWCt//vAH4c M+2mi6E0PjOXNv5F5R+A5Vg4oYAnXFLBay8eg+ss4ffSdV4XA0gRHUVUA4MF11FJ rGJPhvNSOiuhnA2P3gNJd7EMHXLsZedLLHd00N5ZoOrSB9sTs7Q8qUiBnh1cCms/ /amCZBJQV8qZpyutn4lQC575JmGwysmou6Upg1f97GsqCVSIGQle+JjqcKJJ70Qr jjTxg5/JKupcDhvJntfWm17z8dRdScsjzRnpWTNa1QeD48JJGyottbbX739pjtzC afz8RqW3NDI7gwFMHcz6uo5hTsDByXP9NHexIDmgoDjxVu/NGOrQTegjRdFiE3k8 AZ1VNQZoa+nwp8TDxbc7XMxW/fg+noTZw3E+IvExw+jo+x0HSiYnsL3VxGlDBPlA b4D9DkTR2z+u5EAMztnC =C3go -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux Pull clock controller fixes from Michael Turquette: "Two small fixes for the Zynq clock controller introduced in 3.11-rc1 and another Exynos clock patch which fixes a regression that prevents the video pipeline from functioning on that platform" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux: clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocks clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes clk/zynq/clkc: Add dedicated spinlock for the SWDT
This commit is contained in:
Linus Torvalds
Коммит
0f7dd1aa8f
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@ -581,11 +581,15 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
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DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
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DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
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DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
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DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
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DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
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DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
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CLK_GET_RATE_NOCACHE, 0),
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DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
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CLK_GET_RATE_NOCACHE, 0),
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DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
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DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
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DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
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DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
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4, 3, CLK_GET_RATE_NOCACHE, 0),
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DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
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8, 3, CLK_GET_RATE_NOCACHE, 0),
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DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
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};
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@ -863,57 +867,57 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
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GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
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E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
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GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
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};
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@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(armpll_lock);
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static DEFINE_SPINLOCK(ddrpll_lock);
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static DEFINE_SPINLOCK(iopll_lock);
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static DEFINE_SPINLOCK(armclk_lock);
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static DEFINE_SPINLOCK(swdtclk_lock);
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static DEFINE_SPINLOCK(ddrclk_lock);
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static DEFINE_SPINLOCK(dciclk_lock);
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static DEFINE_SPINLOCK(gem0clk_lock);
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@ -293,7 +294,7 @@ static void __init zynq_clk_setup(struct device_node *np)
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}
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clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
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swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
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SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
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SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock);
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/* DDR clocks */
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clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
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@ -364,8 +365,9 @@ static void __init zynq_clk_setup(struct device_node *np)
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CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&gem0clk_lock);
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clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
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SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
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clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
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CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
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&gem0clk_lock);
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clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
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"gem0_emio_mux", CLK_SET_RATE_PARENT,
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SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
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@ -386,8 +388,9 @@ static void __init zynq_clk_setup(struct device_node *np)
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CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&gem1clk_lock);
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clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
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SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
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clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
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CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
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&gem1clk_lock);
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clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
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"gem1_emio_mux", CLK_SET_RATE_PARENT,
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SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
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