From 7828494f78e4596e24d3fcce5bb2872f42ab9632 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:56 +0100 Subject: [PATCH 01/24] ARM: dts: stm32: Add alternate pinmux for ethernet0 pins Add another mux option for ethernet0 pins, this is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and then fed back via PA1 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index f0d66d8c6e3b..4890e8d4353b 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -379,6 +379,40 @@ }; }; + ethernet0_rmii_pins_c: rmii-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ From f6f39403ce6120226308124b80af7f18731192e7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:57 +0100 Subject: [PATCH 02/24] ARM: dts: stm32: Add alternate pinmux for mco2 pins Add pinmux option for MCO2 pin. This is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 4890e8d4353b..3c44a04c13fb 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -923,6 +923,21 @@ }; }; + mco2_pins_a: mco2-0 { + pins { + pinmux = ; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = ; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ From 73ab99aad50cd05ed0bc230aea39c733ebb9711d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:58 +0100 Subject: [PATCH 03/24] ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 22 ++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 83e2c87713f8..238a611192e7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -446,6 +445,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; From efaa952f95929554c677d6d236d8641e93aa0bc2 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Fri, 11 Mar 2022 13:14:48 +0100 Subject: [PATCH 04/24] ARM: dts: stm32: fix pinctrl node name warnings (MCU soc) The recent addition pinctrl.yaml in commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml") resulted in some node name warnings. Fix the node names to the preferred 'pinctrl'. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 2 +- arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 2 +- arch/arm/boot/dts/stm32h743.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 155d9ffacc83..500bcc302d42 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -45,7 +45,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index 1cf8a23c2644..8f37aefa7315 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 6e42ca2dada2..91dde07a38ba 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -583,7 +583,7 @@ status = "disabled"; }; - pinctrl: pin-controller@58020000 { + pinctrl: pinctrl@58020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; From 42da167bbd2910e4ac6334174f6dc273e079fb91 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Fri, 11 Mar 2022 13:13:23 +0100 Subject: [PATCH 05/24] ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) The recent addition pinctrl.yaml in commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml") resulted in some node name warnings. Fix the node names to the preferred 'pinctrl'. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 +- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 1708c79b5254..294c4aec3342 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -239,7 +239,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index f9aa9af31efd..7fdc324b3cf9 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1623,7 +1623,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; @@ -1754,7 +1754,7 @@ }; }; - pinctrl_z: pin-controller-z@54004000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; From ef2d90708883f4025a801feb0ba8411a7a4387e1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 25 Mar 2022 18:58:51 +0100 Subject: [PATCH 06/24] ARM: dts: stm32: Fix PHY post-reset delay on Avenger96 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per KSZ9031RNX PHY datasheet FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2: After the de-assertion of reset, wait a minimum of 100 μs before starting programming on the MIIM (MDC/MDIO) interface. Add 1ms post-reset delay to guarantee this figure. Fixes: 010ca9fe500bf ("ARM: dts: stm32: Add missing ethernet PHY reset on AV96") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 61e17f44ce81..76c54b006d87 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -141,6 +141,7 @@ compatible = "snps,dwmac-mdio"; reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; reset-delay-us = <1000>; + reset-post-delay-us = <1000>; phy0: ethernet-phy@7 { reg = <7>; From cc2b6b6fa4ced56faaf5bc7ad2e26fee08bfd1f7 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Thu, 7 Apr 2022 18:20:41 +0200 Subject: [PATCH 07/24] ARM: dts: stm32: add RTC node on stm32mp131 Add RTC node with compatible, clock, and interrupt properties on stm32mp131. Add clk_rtc_k fixed clock for RTC. Signed-off-by: Gabriel Fernandez Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 294c4aec3342..58647396704f 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -75,6 +75,12 @@ compatible = "fixed-clock"; clock-frequency = <99000000>; }; + + clk_rtc_k: clk-rtc-k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; }; intc: interrupt-controller@a0021000 { @@ -218,6 +224,15 @@ status = "disabled"; }; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>, <&clk_rtc_k>; + clock-names = "pclk", "rtc_ck"; + status = "disabled"; + }; + bsec: efuse@5c005000 { compatible = "st,stm32mp15-bsec"; reg = <0x5c005000 0x400>; From 448fb6ea127ce64efca1d91bef61e587583c2afe Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Thu, 7 Apr 2022 18:20:42 +0200 Subject: [PATCH 08/24] ARM: dts: stm32: enable RTC support on stm32mp135f-dk Enables the support of RTC on stm32mp135f-dk board. Signed-off-by: Gabriel Fernandez Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index ee100d108ea2..aefa25ee897d 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -37,6 +37,10 @@ status = "okay"; }; +&rtc { + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; From bb419dc67bb51d15740df5a775da1de057e4b2fb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Apr 2022 16:04:35 +0200 Subject: [PATCH 09/24] dt-bindings: arm: stm32: narrow DH STM32MP1 SoM boards The bindings for DH STM32MP1 SoM boards allows invalid combinations, e.g. st,stm32mp153 SoC on a dh,stm32mp157c-dhcom-som SoM. Split the enums to properly match valid setups. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/arm/stm32/stm32.yaml | 37 +++++++++++-------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index fa0a1b84122e..2f83f2760e6a 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -14,21 +14,6 @@ properties: const: "/" compatible: oneOf: - - description: DH STM32MP1 SoM based Boards - items: - - enum: - - arrow,stm32mp157a-avenger96 # Avenger96 - - dh,stm32mp153c-dhcom-drc02 - - dh,stm32mp157c-dhcom-pdk2 - - dh,stm32mp157c-dhcom-picoitx - - enum: - - dh,stm32mp153c-dhcom-som - - dh,stm32mp157a-dhcor-som - - dh,stm32mp157c-dhcom-som - - enum: - - st,stm32mp153 - - st,stm32mp157 - - description: emtrion STM32MP1 Argon based Boards items: - const: emtrion,stm32mp157c-emsbc-argon @@ -65,6 +50,13 @@ properties: - enum: - st,stm32mp135f-dk - const: st,stm32mp135 + + - description: DH STM32MP153 SoM based Boards + items: + - const: dh,stm32mp153c-dhcom-drc02 + - const: dh,stm32mp153c-dhcom-som + - const: st,stm32mp153 + - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box @@ -79,6 +71,21 @@ properties: - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - const: dh,stm32mp157a-dhcor-som + - const: st,stm32mp157 + + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - dh,stm32mp157c-dhcom-pdk2 + - dh,stm32mp157c-dhcom-picoitx + - const: dh,stm32mp157c-dhcom-som + - const: st,stm32mp157 + - description: Engicam i.Core STM32MP1 SoM based Boards items: - enum: From 5d68f9798d7da8a1004d3d09e56dc7b379700016 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Apr 2022 16:04:36 +0200 Subject: [PATCH 10/24] dt-bindings: arm: stm32: correct blank lines Correct blank lines to precesily separate entries. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 2f83f2760e6a..80b29f6903f0 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -64,8 +64,8 @@ properties: - st,stm32mp157c-ed1 - st,stm32mp157a-dk1 - st,stm32mp157c-dk2 - - const: st,stm32mp157 + - items: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 @@ -110,6 +110,7 @@ properties: - const: oct,stm32mp15xx-osd32 - enum: - st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards items: - enum: From c70bb467fb211fadd2c1360892a498330d8a94a6 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:08 +0200 Subject: [PATCH 11/24] dt-bindings: arm: stm32: Add compatible strings for Protonic T1L boards This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 80b29f6903f0..a93c60241f28 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -51,6 +51,14 @@ properties: - st,stm32mp135f-dk - const: st,stm32mp135 + - description: ST STM32MP151 based Boards + items: + - enum: + - prt,prtt1a # Protonic PRTT1A + - prt,prtt1c # Protonic PRTT1C + - prt,prtt1s # Protonic PRTT1S + - const: st,stm32mp151 + - description: DH STM32MP153 SoM based Boards items: - const: dh,stm32mp153c-dhcom-drc02 From 94de07e5565be51d91dd91dcae6ede54c0f9be27 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:09 +0200 Subject: [PATCH 12/24] dt-bindings: net: silabs,wfx: add prt,prtt1c-wfm200 antenna variant Add compatible for wfm200 antenna configuration variant for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/staging/net/wireless/silabs,wfx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml index 105725a127ab..ce107fe45d7c 100644 --- a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml @@ -39,6 +39,7 @@ properties: compatible: items: - enum: + - prt,prtt1c-wfm200 # Protonic PRTT1C Board - silabs,brd4001a # WGM160P Evaluation Board - silabs,brd8022a # WF200 Evaluation Board - silabs,brd8023a # WFM200 Evaluation Board From 9ad65d245b7b918353d4b1279e7d3190a0e087fd Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:10 +0200 Subject: [PATCH 13/24] ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group Add spi1-1 pingroup as preparation for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 3c44a04c13fb..6052243ad81c 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2261,4 +2261,19 @@ bias-disable; }; }; + + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; }; From 1a43e9b281c6eaadf788c3bfff3062860ced8e87 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:11 +0200 Subject: [PATCH 14/24] ARM: dts: stm32: add support for Protonic PRTT1x boards This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/stm32mp151a-prtt1a.dts | 52 ++++ arch/arm/boot/dts/stm32mp151a-prtt1c.dts | 304 ++++++++++++++++++++++ arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi | 229 ++++++++++++++++ arch/arm/boot/dts/stm32mp151a-prtt1s.dts | 63 +++++ 5 files changed, 651 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1a.dts create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1c.dts create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1s.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..2585ba8e1293 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1156,6 +1156,9 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ stm32mp135f-dk.dtb \ + stm32mp151a-prtt1a.dtb \ + stm32mp151a-prtt1c.dtb \ + stm32mp151a-prtt1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts new file mode 100644 index 000000000000..75874eafde11 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1A"; + compatible = "prt,prtt1a", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; + +&pwm5_pins_a { + pins { + pinmux = ; /* TIM5_CH1 */ + }; +}; + +&pwm5_sleep_pins_a { + pins { + pinmux = ; /* TIM5_CH1 */ + }; +}; + +&timers5 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts new file mode 100644 index 000000000000..7ecf31263abc --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1C"; + compatible = "prt,prtt1c", "st,stm32mp151"; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + }; +}; + +ðernet0 { + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "", + "", "", "", "", "", "", "", "SPI1_nSS"; +}; + +&gpiod { + gpio-line-names = + "", "", "", "", "", "", "", "", + "WFM_RESET", "", "", "", "", "", "", ""; +}; + +&gpioe { + gpio-line-names = + "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "", + "", "", "", "", "WFM_nIRQ", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "PHY3_nINT", + "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET", + "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", ""; +}; + +&mdio0 { + /* All this DP83TD510E PHYs can't be probed before switch@0 is + * probed so we need to use compatible with PHYid + */ + /* TI DP83TD510E */ + t1l0_phy: ethernet-phy@6 { + compatible = "ethernet-phy-id2000.0181"; + reg = <6>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l1_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.0181"; + reg = <7>; + interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l2_phy: ethernet-phy@10 { + compatible = "ethernet-phy-id2000.0181"; + reg = <10>; + interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* Micrel KSZ9031 */ + rj45_phy: ethernet-phy@2 { + reg = <2>; + interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; +}; + +&qspi { + status = "disabled"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc2_b4_od_pins_a { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + }; +}; + +&sdmmc2_b4_pins_a { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_b4_sleep_pins_a { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_d47_pins_a { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; +}; + +&sdmmc2_d47_sleep_pins_a { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + non-removable; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmc@1 { + compatible = "prt,prtt1c-wfm200", "silabs,wf200"; + reg = <1>; + }; +}; + +&sdmmc3_b4_od_pins_b { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + }; +}; + +&sdmmc3_b4_pins_b { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + }; +}; + +&sdmmc3_b4_sleep_pins_b { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins_b>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "t1l0"; + phy-mode = "rmii"; + phy-handle = <&t1l0_phy>; + }; + + port@1 { + reg = <1>; + label = "t1l1"; + phy-mode = "rmii"; + phy-handle = <&t1l1_phy>; + }; + + port@2 { + reg = <2>; + label = "t1l2"; + phy-mode = "rmii"; + phy-handle = <&t1l2_phy>; + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rj45_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <ðernet0>; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi new file mode 100644 index 000000000000..d865ab5d866b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxad-pinctrl.dtsi" +#include +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + mdio-gpio0 = &mdio0; + serial0 = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + status = "okay"; +}; + +ðernet0_rmii_pins_a { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + ; /* ETH1_RMII_TX_EN */ + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK input */ + ; /* ETH1_RMII_CRS_DV */ + }; +}; + +ðernet0_rmii_sleep_pins_a { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; +}; + +&iwdg2 { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <104000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&qspi_bk1_pins_a { + pins1 { + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_od_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&sdmmc1_b4_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart4_idle_pins_a { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_pins_a { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_sleep_pins_a { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <®_3v3>; +}; + +&usbphyc_port1 { + phy-supply = <®_3v3>; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts new file mode 100644 index 000000000000..ad25929e64e6 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1S"; + compatible = "prt,prtt1s", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + humidity-sensor@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + }; +}; + +&i2c1_pins_a { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; +}; + +&i2c1_sleep_pins_a { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; From 6e82a968b77c7f16a33173485eff2e9a6ae0c6d1 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 3 May 2022 11:06:21 +0200 Subject: [PATCH 15/24] ARM: dts: stm32: add EXTI interrupt-parent to pinctrl node on stm32mp131 Add interrupt-parent property in pinctrl node to use GPIO as IRQ. Signed-off-by: Amelie Delaunay Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 58647396704f..f9ebc47e6421 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -259,6 +259,8 @@ #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; pins-are-numbered; gpioa: gpio@50002000 { From fd91c36fd349f5117cf51c1c9b75f60ac5a7a4fe Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 3 May 2022 11:41:24 +0200 Subject: [PATCH 16/24] ARM: dts: stm32: add blue led (Linux heartbeat) on stm32mp135f-dk The blue led (Linux heartbeat) is connected to the PA14 pin of the stm32mp135f-dk board. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index aefa25ee897d..65acee0f68b7 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include +#include #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -23,6 +25,18 @@ reg = <0xc0000000 0x20000000>; }; + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; From 57012d79fefd56499da681ecd0f94642e8b59992 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 3 May 2022 11:41:33 +0200 Subject: [PATCH 17/24] ARM: dts: stm32: add UserPA13 button on stm32mp135f-dk The PA13 user button is connected to the PA13 pin of the stm32mp135f-dk board. It requires an internal pull-up configuration. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 65acee0f68b7..09d6226d598f 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" @@ -25,6 +26,16 @@ reg = <0xc0000000 0x20000000>; }; + gpio-keys { + compatible = "gpio-keys"; + + user-pa13 { + label = "User-PA13"; + linux,code = ; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + leds { compatible = "gpio-leds"; From 6e5b6ce2053c3a7ba94d93962e66b5240e286279 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 11 Apr 2022 00:05:14 +0200 Subject: [PATCH 18/24] dt-bindings: rcc: Add optional external ethernet RX clock properties Describe optional external ethernet RX clock in the DT binding to fix dtbs_check warnings like: arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dt.yaml: rcc@50000000: 'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Gabriel Fernandez Cc: Rob Herring To: devicetree@vger.kernel.org Acked-by: Gabriel Fernandez Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220410220514.21779-1-marex@denx.de Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index a0ae4867ed27..7a251264582d 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -59,6 +59,14 @@ properties: - st,stm32mp1-rcc - const: syscon + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + reg: maxItems: 1 From 35de4b4b82bcfaa5a33fd02e74a453fc67b3b1ec Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:46 +0200 Subject: [PATCH 19/24] dt-bindings: clock: stm32mp1: describes clocks if "st,stm32mp1-rcc-secure" In case of "st,stm32mp1-rcc-secure" (stm32mp1 clock driver with RCC security support hardened), "clocks" and "clock-names" describe oscillators and are required. Signed-off-by: Alexandre Torgue Reviewed-by: Rob Herring --- .../bindings/clock/st,stm32mp1-rcc.yaml | 42 +++++++++++++++---- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index 7a251264582d..bb0e0b92e907 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -58,14 +58,8 @@ properties: - st,stm32mp1-rcc-secure - st,stm32mp1-rcc - const: syscon - - clocks: - description: - Specifies the external RX clock for ethernet MAC. - maxItems: 1 - - clock-names: - const: ETH_RX_CLK/ETH_REF_CLK + clocks: true + clock-names: true reg: maxItems: 1 @@ -76,6 +70,38 @@ required: - compatible - reg +if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-rcc-secure +then: + properties: + clocks: + description: Specifies oscillators. + maxItems: 5 + + clock-names: + items: + - const: hse + - const: hsi + - const: csi + - const: lse + - const: lsi + required: + - clocks + - clock-names +else: + properties: + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + additionalProperties: false examples: From 9b0df592522c6f86283679436f2eac49bd23cdce Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:47 +0200 Subject: [PATCH 20/24] dt-bindings: clock: stm32mp15: rename CK_SCMI define As we only have one SCMI instance, it's not necessary to add an index to the name. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- include/dt-bindings/clock/stm32mp1-clks.h | 46 +++++++++++------------ 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index e02770b98e6c..25e8cfd43459 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -249,30 +249,26 @@ #define STM32MP1_LAST_CLK 232 /* SCMI clock identifiers */ -#define CK_SCMI0_HSE 0 -#define CK_SCMI0_HSI 1 -#define CK_SCMI0_CSI 2 -#define CK_SCMI0_LSE 3 -#define CK_SCMI0_LSI 4 -#define CK_SCMI0_PLL2_Q 5 -#define CK_SCMI0_PLL2_R 6 -#define CK_SCMI0_MPU 7 -#define CK_SCMI0_AXI 8 -#define CK_SCMI0_BSEC 9 -#define CK_SCMI0_CRYP1 10 -#define CK_SCMI0_GPIOZ 11 -#define CK_SCMI0_HASH1 12 -#define CK_SCMI0_I2C4 13 -#define CK_SCMI0_I2C6 14 -#define CK_SCMI0_IWDG1 15 -#define CK_SCMI0_RNG1 16 -#define CK_SCMI0_RTC 17 -#define CK_SCMI0_RTCAPB 18 -#define CK_SCMI0_SPI6 19 -#define CK_SCMI0_USART1 20 - -#define CK_SCMI1_PLL3_Q 0 -#define CK_SCMI1_PLL3_R 1 -#define CK_SCMI1_MCU 2 +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_PLL2_Q 5 +#define CK_SCMI_PLL2_R 6 +#define CK_SCMI_MPU 7 +#define CK_SCMI_AXI 8 +#define CK_SCMI_BSEC 9 +#define CK_SCMI_CRYP1 10 +#define CK_SCMI_GPIOZ 11 +#define CK_SCMI_HASH1 12 +#define CK_SCMI_I2C4 13 +#define CK_SCMI_I2C6 14 +#define CK_SCMI_IWDG1 15 +#define CK_SCMI_RNG1 16 +#define CK_SCMI_RTC 17 +#define CK_SCMI_RTCAPB 18 +#define CK_SCMI_SPI6 19 +#define CK_SCMI_USART1 20 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ From 5f5d7decf046557876794c5686ee0ccf5907bfde Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:48 +0200 Subject: [PATCH 21/24] dt-bindings: reset: stm32mp15: rename RST_SCMI define As we only have one SCMI instance, it's not necessary to add an index to the name. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- include/dt-bindings/reset/stm32mp1-resets.h | 24 ++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index f3a0ed317835..4ffa7c3612e6 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -107,17 +107,17 @@ #define GPIOK_R 19786 /* SCMI reset domain identifiers */ -#define RST_SCMI0_SPI6 0 -#define RST_SCMI0_I2C4 1 -#define RST_SCMI0_I2C6 2 -#define RST_SCMI0_USART1 3 -#define RST_SCMI0_STGEN 4 -#define RST_SCMI0_GPIOZ 5 -#define RST_SCMI0_CRYP1 6 -#define RST_SCMI0_HASH1 7 -#define RST_SCMI0_RNG1 8 -#define RST_SCMI0_MDMA 9 -#define RST_SCMI0_MCU 10 -#define RST_SCMI0_MCU_HOLD_BOOT 11 +#define RST_SCMI_SPI6 0 +#define RST_SCMI_I2C4 1 +#define RST_SCMI_I2C6 2 +#define RST_SCMI_USART1 3 +#define RST_SCMI_STGEN 4 +#define RST_SCMI_GPIOZ 5 +#define RST_SCMI_CRYP1 6 +#define RST_SCMI_HASH1 7 +#define RST_SCMI_RNG1 8 +#define RST_SCMI_MDMA 9 +#define RST_SCMI_MCU 10 +#define RST_SCMI_MCU_HOLD_BOOT 11 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ From 40b4157dbd8cfecbfafdf64aaa562c140a4a5ef1 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:50 +0200 Subject: [PATCH 22/24] ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 Enable optee and SCMI clocks/reset protocols support. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 7fdc324b3cf9..1b2fd3426a81 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -115,6 +115,33 @@ status = "disabled"; }; + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + status = "disabled"; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -122,6 +149,20 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + status = "disabled"; + }; + }; + timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; From 8e14ebb1f08f036539c8cd362a9fd173c4befa2a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:51 +0200 Subject: [PATCH 23/24] dt-bindings: arm: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) Add a "secure" version based on SCMI of STM32 boards. Only boards provided by STMicroelectronics are concerned: -STM32MP157A-DK1 -STM32MP157C-DK2 -STM32MP157C-ED1 -STM32MP157C-EV1 Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- .../devicetree/bindings/arm/stm32/stm32.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index a93c60241f28..8b31565fee59 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -75,6 +75,23 @@ properties: - const: st,stm32mp157 - items: + - const: st,stm32mp157a-dk1-scmi + - const: st,stm32mp157a-dk1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-dk2-scmi + - const: st,stm32mp157c-dk2 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ed1-scmi + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1-scmi - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 From 5b7e58313a77e951850586cfaa9f5d60122f908f Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:52 +0200 Subject: [PATCH 24/24] ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) Add a "secure" version based on SCMI of STM32 boards. Only boards provided by STMicroelectronics are concerned: -STM32MP157A-DK1 -STM32MP157C-DK2 -STM32MP157C-ED1 -STM32MP157C-EV1 Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 4 + arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 86 ++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 95 ++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 91 +++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 100 +++++++++++++++++++++ 5 files changed, 376 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2585ba8e1293..11bedf200a86 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1163,6 +1163,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ stm32mp157a-iot-box.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ @@ -1173,9 +1174,12 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ stm32mp157c-emsbc-argon.dtb \ stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts new file mode 100644 index 000000000000..e3d3f3f30c7d --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; + compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts new file mode 100644 index 000000000000..45dcd299aa9e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; + compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts new file mode 100644 index 000000000000..458e0ca3cded --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ed1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; + compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts new file mode 100644 index 000000000000..df9c113edb4b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", + "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m_can1 { + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +};