gpio/sx150x: Do not access I2C from mask/unmask functions
irq_chip->irq_mask/unmask are called with interrupts disabled and irq_desc->lock held. So we cannot access i2c from this context. That's what irq_bus_sync_unlock() is for. Store the masked information in the chip data structure and update the i2c bus from the irq_bus_sync_unlock() callback. This does not need a while(pending) loop because the update to this is always serialized via the bus lock, so we never have more than one pin update pending. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Gregory Bean <gbean@codeaurora.org> Cc: Jean Delvare <khali@linux-fr.org> Cc: Lennert Buytenhek <buytenh@secretlab.ca> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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0b782531c0
Коммит
0ff56cd85a
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@ -25,6 +25,8 @@
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#include <linux/workqueue.h>
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#include <linux/i2c/sx150x.h>
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#define NO_UPDATE_PENDING -1
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struct sx150x_device_data {
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u8 reg_pullup;
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u8 reg_pulldn;
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@ -47,8 +49,11 @@ struct sx150x_chip {
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const struct sx150x_device_data *dev_cfg;
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int irq_summary;
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int irq_base;
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int irq_update;
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u32 irq_sense;
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unsigned long irq_set_type_pending;
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u32 irq_masked;
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u32 dev_sense;
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u32 dev_masked;
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struct irq_chip irq_chip;
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struct mutex lock;
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};
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@ -312,9 +317,8 @@ static void sx150x_irq_mask(struct irq_data *d)
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chip = container_of(ic, struct sx150x_chip, irq_chip);
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n = d->irq - chip->irq_base;
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sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
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sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
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chip->irq_masked |= (1 << n);
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chip->irq_update = n;
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}
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static void sx150x_irq_unmask(struct irq_data *d)
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@ -326,9 +330,8 @@ static void sx150x_irq_unmask(struct irq_data *d)
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chip = container_of(ic, struct sx150x_chip, irq_chip);
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n = d->irq - chip->irq_base;
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sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
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sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
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chip->irq_sense >> (n * 2));
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chip->irq_masked &= ~(1 << n);
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chip->irq_update = n;
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}
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static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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@ -350,7 +353,7 @@ static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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chip->irq_sense &= ~(3UL << (n * 2));
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chip->irq_sense |= val << (n * 2);
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chip->irq_set_type_pending |= BIT(n);
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chip->irq_update = n;
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return 0;
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}
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@ -404,15 +407,29 @@ static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
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chip = container_of(ic, struct sx150x_chip, irq_chip);
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while (chip->irq_set_type_pending) {
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n = __ffs(chip->irq_set_type_pending);
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chip->irq_set_type_pending &= ~BIT(n);
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if (!(irq_to_desc(n + chip->irq_base)->status & IRQ_MASKED))
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sx150x_write_cfg(chip, n, 2,
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chip->dev_cfg->reg_sense,
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if (chip->irq_update == NO_UPDATE_PENDING)
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goto out;
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n = chip->irq_update;
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chip->irq_update = NO_UPDATE_PENDING;
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/* Avoid updates if nothing changed */
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if (chip->dev_sense == chip->irq_sense &&
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chip->dev_sense == chip->irq_masked)
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goto out;
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chip->dev_sense = chip->irq_sense;
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chip->dev_masked = chip->irq_masked;
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if (chip->irq_masked & (1 << n)) {
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sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
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sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
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} else {
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sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
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sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
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chip->irq_sense >> (n * 2));
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}
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out:
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mutex_unlock(&chip->lock);
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}
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@ -445,8 +462,11 @@ static void sx150x_init_chip(struct sx150x_chip *chip,
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chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
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chip->irq_summary = -1;
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chip->irq_base = -1;
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chip->irq_masked = ~0;
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chip->irq_sense = 0;
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chip->irq_set_type_pending = 0;
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chip->dev_masked = ~0;
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chip->dev_sense = 0;
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chip->irq_update = NO_UPDATE_PENDING;
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}
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static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
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