Merge tag 'amd-drm-fixes-6.0-2022-08-25' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.0-2022-08-25: amdgpu: - GFX 11.0 fixes - PSP XGMI handling fixes - GFX9 fix for compute-only IPs - Drop duplicated function call - Fix warning due to missing header - NBIO 7.7 fixes - DCN 3.1.4 fixes - SDMA 6.0 fixes - SMU 13.0 fixes - Arcturus GPUVM page table fix - MMHUB 1.0 fix amdkfd: - GC 10.3.7 fix radeon: - Delayed work flush fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220825181243.5853-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
Коммит
100d0ae82b
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@ -2456,12 +2456,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
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if (!hive->reset_domain ||
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!amdgpu_reset_get_reset_domain(hive->reset_domain)) {
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r = -ENOENT;
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amdgpu_put_xgmi_hive(hive);
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goto init_failed;
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}
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/* Drop the early temporary reset domain we created for device */
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amdgpu_reset_put_reset_domain(adev->reset_domain);
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adev->reset_domain = hive->reset_domain;
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amdgpu_put_xgmi_hive(hive);
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}
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}
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@ -4413,8 +4415,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
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retry:
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amdgpu_amdkfd_pre_reset(adev);
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amdgpu_amdkfd_pre_reset(adev);
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if (from_hypervisor)
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r = amdgpu_virt_request_full_gpu(adev, true);
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else
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@ -2641,6 +2641,9 @@ static int psp_hw_fini(void *handle)
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psp_rap_terminate(psp);
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psp_dtm_terminate(psp);
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psp_hdcp_terminate(psp);
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if (adev->gmc.xgmi.num_physical_nodes > 1)
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psp_xgmi_terminate(psp);
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}
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psp_asd_terminate(psp);
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@ -742,7 +742,7 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
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amdgpu_put_xgmi_hive(hive);
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}
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return psp_xgmi_terminate(&adev->psp);
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return 0;
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}
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static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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@ -131,6 +131,8 @@ static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
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bool all_hub, uint8_t dst_sel);
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static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);
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static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);
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static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
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bool enable);
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static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
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{
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@ -1139,6 +1141,7 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
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.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
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.select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
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.init_spm_golden = &gfx_v11_0_init_spm_golden_registers,
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.update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
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};
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static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
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@ -5182,9 +5185,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
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data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
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WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
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/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
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if (adev->sdma.num_instances > 1) {
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data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
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data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
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WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
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}
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} else {
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/* Program RLC_CGCG_CGLS_CTRL */
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def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
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@ -5213,10 +5219,13 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
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data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
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WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
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/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
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if (adev->sdma.num_instances > 1) {
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data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
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data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
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WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
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}
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}
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}
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static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
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@ -5328,8 +5337,7 @@ static int gfx_v11_0_set_powergating_state(void *handle,
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break;
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case IP_VERSION(11, 0, 1):
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gfx_v11_cntl_pg(adev, enable);
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/* TODO: Enable this when GFXOFF is ready */
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// amdgpu_gfx_off_ctrl(adev, enable);
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amdgpu_gfx_off_ctrl(adev, enable);
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break;
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default:
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break;
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@ -2587,6 +2587,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
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gfx_v9_0_tiling_mode_table_init(adev);
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if (adev->gfx.num_gfx_rings)
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gfx_v9_0_setup_rb(adev);
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gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
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adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
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@ -176,6 +176,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
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WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
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tmp = mmVM_L2_CNTL3_DEFAULT;
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if (adev->gmc.translate_further) {
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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@ -295,9 +295,17 @@ static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
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static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
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unsigned int num_level, block_size;
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uint32_t tmp;
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int i;
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num_level = adev->vm_manager.num_level;
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block_size = adev->vm_manager.block_size;
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if (adev->gmc.translate_further)
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num_level -= 1;
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else
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block_size -= 9;
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for (i = 0; i <= 14; i++) {
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tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
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hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
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@ -305,7 +313,7 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
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ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
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PAGE_TABLE_DEPTH,
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adev->vm_manager.num_level);
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num_level);
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tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
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@ -323,7 +331,7 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
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EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
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PAGE_TABLE_BLOCK_SIZE,
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adev->vm_manager.block_size - 9);
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block_size);
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/* Send no-retry XNACK on fault to suppress VM fault storm. */
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tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
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RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
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@ -247,6 +247,81 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
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}
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static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
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return;
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def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
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if (enable) {
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data |= (BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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} else {
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data &= ~(BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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}
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if (def != data)
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WREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL, data);
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}
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static void nbio_v7_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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return;
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def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
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if (enable)
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data |= BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
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else
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data &= ~BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
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if (def != data)
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WREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2, data);
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def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1);
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if (enable) {
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data |= (BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
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} else {
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data &= ~(BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
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}
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if (def != data)
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WREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1, data);
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}
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static void nbio_v7_7_get_clockgating_state(struct amdgpu_device *adev,
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u64 *flags)
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{
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uint32_t data;
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/* AMD_CG_SUPPORT_BIF_MGCG */
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data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
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if (data & BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_MGCG;
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/* AMD_CG_SUPPORT_BIF_LS */
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data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
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if (data & BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_LS;
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}
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const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
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.get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,
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.get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,
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@ -262,6 +337,9 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
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.enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
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.enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
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.ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
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.update_medium_grain_clock_gating = nbio_v7_7_update_medium_grain_clock_gating,
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.update_medium_grain_light_sleep = nbio_v7_7_update_medium_grain_light_sleep,
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.get_clockgating_state = nbio_v7_7_get_clockgating_state,
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.ih_control = nbio_v7_7_ih_control,
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.init_registers = nbio_v7_7_init_registers,
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};
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@ -494,6 +494,20 @@ static void soc21_pre_asic_init(struct amdgpu_device *adev)
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{
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}
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static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
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bool enter)
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{
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if (enter)
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amdgpu_gfx_rlc_enter_safe_mode(adev);
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else
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amdgpu_gfx_rlc_exit_safe_mode(adev);
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if (adev->gfx.funcs->update_perfmon_mgcg)
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adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
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return 0;
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}
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static const struct amdgpu_asic_funcs soc21_asic_funcs =
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{
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.read_disabled_bios = &soc21_read_disabled_bios,
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@ -513,6 +527,7 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs =
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.supports_baco = &amdgpu_dpm_is_baco_supported,
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.pre_asic_init = &soc21_pre_asic_init,
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.query_video_codecs = &soc21_query_video_codecs,
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.update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
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};
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static int soc21_common_early_init(void *handle)
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@ -603,6 +618,8 @@ static int soc21_common_early_init(void *handle)
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AMD_CG_SUPPORT_ATHUB_MGCG |
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AMD_CG_SUPPORT_ATHUB_LS |
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AMD_CG_SUPPORT_IH_CG |
|
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AMD_CG_SUPPORT_BIF_MGCG |
|
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AMD_CG_SUPPORT_BIF_LS |
|
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AMD_CG_SUPPORT_VCN_MGCG |
|
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AMD_CG_SUPPORT_JPEG_MGCG;
|
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adev->pg_flags =
|
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|
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@ -702,6 +719,7 @@ static int soc21_common_set_clockgating_state(void *handle,
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switch (adev->ip_versions[NBIO_HWIP][0]) {
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case IP_VERSION(4, 3, 0):
|
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case IP_VERSION(4, 3, 1):
|
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case IP_VERSION(7, 7, 0):
|
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adev->nbio.funcs->update_medium_grain_clock_gating(adev,
|
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state == AMD_CG_STATE_GATE);
|
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adev->nbio.funcs->update_medium_grain_light_sleep(adev,
|
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|
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@ -709,10 +727,6 @@ static int soc21_common_set_clockgating_state(void *handle,
|
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adev->hdp.funcs->update_clock_gating(adev,
|
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state == AMD_CG_STATE_GATE);
|
||||
break;
|
||||
case IP_VERSION(7, 7, 0):
|
||||
adev->hdp.funcs->update_clock_gating(adev,
|
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state == AMD_CG_STATE_GATE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -382,12 +382,8 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
|
|||
f2g = &gfx_v10_3_kfd2kgd;
|
||||
break;
|
||||
case IP_VERSION(10, 3, 6):
|
||||
gfx_target_version = 100306;
|
||||
if (!vf)
|
||||
f2g = &gfx_v10_3_kfd2kgd;
|
||||
break;
|
||||
case IP_VERSION(10, 3, 7):
|
||||
gfx_target_version = 100307;
|
||||
gfx_target_version = 100306;
|
||||
if (!vf)
|
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f2g = &gfx_v10_3_kfd2kgd;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#include "dal_asic_id.h"
|
||||
#include "amdgpu_display.h"
|
||||
#include "amdgpu_dm_trace.h"
|
||||
#include "amdgpu_dm_plane.h"
|
||||
#include "gc/gc_11_0_0_offset.h"
|
||||
#include "gc/gc_11_0_0_sh_mask.h"
|
||||
|
||||
|
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@ -149,12 +150,12 @@ static void add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_
|
|||
*size += 1;
|
||||
}
|
||||
|
||||
bool modifier_has_dcc(uint64_t modifier)
|
||||
static bool modifier_has_dcc(uint64_t modifier)
|
||||
{
|
||||
return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
|
||||
}
|
||||
|
||||
unsigned modifier_gfx9_swizzle_mode(uint64_t modifier)
|
||||
static unsigned modifier_gfx9_swizzle_mode(uint64_t modifier)
|
||||
{
|
||||
if (modifier == DRM_FORMAT_MOD_LINEAR)
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -36,17 +36,9 @@ int fill_dc_scaling_info(struct amdgpu_device *adev,
|
|||
const struct drm_plane_state *state,
|
||||
struct dc_scaling_info *scaling_info);
|
||||
|
||||
void get_min_max_dc_plane_scaling(struct drm_device *dev,
|
||||
struct drm_framebuffer *fb,
|
||||
int *min_downscale, int *max_upscale);
|
||||
|
||||
int dm_plane_helper_check_state(struct drm_plane_state *state,
|
||||
struct drm_crtc_state *new_crtc_state);
|
||||
|
||||
bool modifier_has_dcc(uint64_t modifier);
|
||||
|
||||
unsigned int modifier_gfx9_swizzle_mode(uint64_t modifier);
|
||||
|
||||
int fill_plane_buffer_attributes(struct amdgpu_device *adev,
|
||||
const struct amdgpu_framebuffer *afb,
|
||||
const enum surface_pixel_format format,
|
||||
|
|
|
|||
|
|
@ -1750,6 +1750,7 @@ static bool dcn314_resource_construct(
|
|||
dc->caps.post_blend_color_processing = true;
|
||||
dc->caps.force_dp_tps4_for_cp2520 = true;
|
||||
dc->caps.dp_hpo = true;
|
||||
dc->caps.dp_hdmi21_pcon_support = true;
|
||||
dc->caps.edp_dsc_support = true;
|
||||
dc->caps.extended_aux_timeout_support = true;
|
||||
dc->caps.dmcub_support = true;
|
||||
|
|
|
|||
|
|
@ -15243,6 +15243,8 @@
|
|||
#define regBIF0_PCIE_TX_TRACKING_ADDR_HI_BASE_IDX 5
|
||||
#define regBIF0_PCIE_TX_TRACKING_CTRL_STATUS 0x420186
|
||||
#define regBIF0_PCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX 5
|
||||
#define regBIF0_PCIE_TX_POWER_CTRL_1 0x420187
|
||||
#define regBIF0_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
|
||||
#define regBIF0_PCIE_TX_CTRL_4 0x42018b
|
||||
#define regBIF0_PCIE_TX_CTRL_4_BASE_IDX 5
|
||||
#define regBIF0_PCIE_TX_STATUS 0x420194
|
||||
|
|
|
|||
|
|
@ -85627,6 +85627,19 @@
|
|||
#define BIF0_PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL
|
||||
#define BIF0_PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L
|
||||
#define BIF0_PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L
|
||||
//BIF0_PCIE_TX_POWER_CTRL_1
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN__SHIFT 0x0
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_DS_EN__SHIFT 0x1
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_SD_EN__SHIFT 0x2
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN__SHIFT 0x3
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_DS_EN__SHIFT 0x4
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_SD_EN__SHIFT 0x5
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_DS_EN_MASK 0x00000002L
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_SD_EN_MASK 0x00000004L
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_DS_EN_MASK 0x00000010L
|
||||
#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_SD_EN_MASK 0x00000020L
|
||||
//BIF0_PCIE_TX_CTRL_4
|
||||
#define BIF0_PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW__SHIFT 0x0
|
||||
#define BIF0_PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW_MASK 0x0000000FL
|
||||
|
|
|
|||
|
|
@ -24,12 +24,8 @@
|
|||
#ifndef SMU13_DRIVER_IF_V13_0_0_H
|
||||
#define SMU13_DRIVER_IF_V13_0_0_H
|
||||
|
||||
// *** IMPORTANT ***
|
||||
// PMFW TEAM: Always increment the interface version on any change to this file
|
||||
#define SMU13_DRIVER_IF_VERSION 0x23
|
||||
|
||||
//Increment this version if SkuTable_t or BoardTable_t change
|
||||
#define PPTABLE_VERSION 0x1D
|
||||
#define PPTABLE_VERSION 0x22
|
||||
|
||||
#define NUM_GFXCLK_DPM_LEVELS 16
|
||||
#define NUM_SOCCLK_DPM_LEVELS 8
|
||||
|
|
@ -1193,8 +1189,17 @@ typedef struct {
|
|||
// SECTION: Advanced Options
|
||||
uint32_t DebugOverrides;
|
||||
|
||||
// Section: Total Board Power idle vs active coefficients
|
||||
uint8_t TotalBoardPowerSupport;
|
||||
uint8_t TotalBoardPowerPadding[3];
|
||||
|
||||
int16_t TotalIdleBoardPowerM;
|
||||
int16_t TotalIdleBoardPowerB;
|
||||
int16_t TotalBoardPowerM;
|
||||
int16_t TotalBoardPowerB;
|
||||
|
||||
// SECTION: Sku Reserved
|
||||
uint32_t Spare[64];
|
||||
uint32_t Spare[61];
|
||||
|
||||
// Padding for MMHUB - do not modify this
|
||||
uint32_t MmHubPadding[8];
|
||||
|
|
@ -1259,7 +1264,8 @@ typedef struct {
|
|||
// SECTION: Clock Spread Spectrum
|
||||
|
||||
// UCLK Spread Spectrum
|
||||
uint16_t UclkSpreadPadding;
|
||||
uint8_t UclkTrainingModeSpreadPercent;
|
||||
uint8_t UclkSpreadPadding;
|
||||
uint16_t UclkSpreadFreq; // kHz
|
||||
|
||||
// UCLK Spread Spectrum
|
||||
|
|
@ -1272,11 +1278,7 @@ typedef struct {
|
|||
|
||||
// Section: Memory Config
|
||||
uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e
|
||||
uint8_t PaddingMem1[3];
|
||||
|
||||
// Section: Total Board Power
|
||||
uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
|
||||
uint16_t BoardPowerPadding;
|
||||
uint8_t PaddingMem1[7];
|
||||
|
||||
// SECTION: UMC feature flags
|
||||
uint8_t HsrEnabled;
|
||||
|
|
@ -1375,8 +1377,11 @@ typedef struct {
|
|||
uint16_t Vcn1ActivityPercentage ;
|
||||
|
||||
uint32_t EnergyAccumulator;
|
||||
uint16_t AverageSocketPower ;
|
||||
uint16_t AverageSocketPower;
|
||||
uint16_t AverageTotalBoardPower;
|
||||
|
||||
uint16_t AvgTemperature[TEMP_COUNT];
|
||||
uint16_t TempPadding;
|
||||
|
||||
uint8_t PcieRate ;
|
||||
uint8_t PcieWidth ;
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
#define SMU13_DRIVER_IF_VERSION_ALDE 0x08
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x05
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2C
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2E
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
|
||||
|
||||
#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
|
||||
|
|
|
|||
|
|
@ -1605,6 +1605,9 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend,
|
|||
if (r) {
|
||||
/* delay GPU reset to resume */
|
||||
radeon_fence_driver_force_completion(rdev, i);
|
||||
} else {
|
||||
/* finish executing delayed work */
|
||||
flush_delayed_work(&rdev->fence_drv[i].lockup_work);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
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