Merge branch 'r8169-improve-pll-power-down-handling'
Heiner Kallweit says: ==================== r8169: improve PLL power-down handling This series includes improvements to handling of PLL power-down. ==================== Link: https://lore.kernel.org/r/1608dfa3-c4a5-0e92-31f7-76674b3c173a@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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101c59b8f6
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@ -261,6 +261,9 @@ enum rtl8168_8101_registers {
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#define CSIAR_BYTE_ENABLE 0x0000f000
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#define CSIAR_ADDR_MASK 0x00000fff
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PMCH = 0x6f,
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#define D3COLD_NO_PLL_DOWN BIT(7)
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#define D3HOT_NO_PLL_DOWN BIT(6)
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#define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
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EPHYAR = 0x80,
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#define EPHYAR_FLAG 0x80000000
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#define EPHYAR_WRITE_CMD 0x80000000
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@ -1250,6 +1253,22 @@ static bool r8168_check_dash(struct rtl8169_private *tp)
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}
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}
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static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
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{
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
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case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
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case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
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if (enable)
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
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else
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
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break;
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default:
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break;
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}
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}
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static void rtl_reset_packet_filter(struct rtl8169_private *tp)
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{
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rtl_eri_clear_bits(tp, 0xdc, BIT(0));
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@ -1416,6 +1435,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
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rtl_lock_config_regs(tp);
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device_set_wakeup_enable(tp_to_dev(tp), wolopts);
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rtl_set_d3_pll_down(tp, !wolopts);
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tp->dev->wol_enabled = wolopts ? 1 : 0;
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}
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@ -2209,7 +2229,7 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
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}
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}
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static void rtl_pll_power_down(struct rtl8169_private *tp)
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static void rtl_prepare_power_down(struct rtl8169_private *tp)
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{
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if (r8168_check_dash(tp))
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return;
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@ -2221,41 +2241,7 @@ static void rtl_pll_power_down(struct rtl8169_private *tp)
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if (device_may_wakeup(tp_to_dev(tp))) {
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phy_speed_down(tp->phydev, false);
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rtl_wol_suspend_quirk(tp);
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return;
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}
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
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case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
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case RTL_GIGA_MAC_VER_37:
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case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_43 ... RTL_GIGA_MAC_VER_63:
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
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break;
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default:
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break;
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}
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}
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static void rtl_pll_power_up(struct rtl8169_private *tp)
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{
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
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case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
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case RTL_GIGA_MAC_VER_37:
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case RTL_GIGA_MAC_VER_39:
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case RTL_GIGA_MAC_VER_43:
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
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break;
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case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_44 ... RTL_GIGA_MAC_VER_63:
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
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break;
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default:
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break;
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}
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phy_resume(tp->phydev);
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}
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static void rtl_init_rxcfg(struct rtl8169_private *tp)
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@ -4613,12 +4599,12 @@ static void rtl8169_down(struct rtl8169_private *tp)
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rtl8169_cleanup(tp, true);
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rtl_pll_power_down(tp);
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rtl_prepare_power_down(tp);
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}
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static void rtl8169_up(struct rtl8169_private *tp)
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{
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rtl_pll_power_up(tp);
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phy_resume(tp->phydev);
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rtl8169_init_phy(tp);
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napi_enable(&tp->napi);
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set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
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@ -5333,6 +5319,8 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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/* configure chip for default features */
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rtl8169_set_features(dev, dev->features);
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rtl_set_d3_pll_down(tp, true);
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jumbo_max = rtl_jumbo_max(tp);
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if (jumbo_max)
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dev->max_mtu = jumbo_max;
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@ -5353,9 +5341,6 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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return rc;
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/* chip gets powered up in rtl_open() */
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rtl_pll_power_down(tp);
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rc = register_netdev(dev);
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if (rc)
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return rc;
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