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drm/radeon: refactor SI tiling table initialization 

Simplify the control flow of si_tiling_mode_table_init() similar to how
it was done in gfx_v7_0.c and gfx_v8_0.c.

Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Josh Poimboeuf 2016-03-11 08:18:24 -06:00 коммит произвёл Alex Deucher
Родитель f0e201f2d3
Коммит 102534b085
1 изменённых файлов: 439 добавлений и 486 удалений
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925
drivers/gpu/drm/radeon/si.c
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@ -2442,8 +2442,10 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
*/ */
static void si_tiling_mode_table_init(struct radeon_device *rdev) static void si_tiling_mode_table_init(struct radeon_device *rdev)
{ {
const u32 num_tile_mode_states = 32; u32 *tile = rdev->config.si.tile_mode_array;
u32 reg_offset, gb_tile_moden, split_equal_to_row_size; const u32 num_tile_mode_states =
ARRAY_SIZE(rdev->config.si.tile_mode_array);
u32 reg_offset, split_equal_to_row_size;
switch (rdev->config.si.mem_row_size_in_kb) { switch (rdev->config.si.mem_row_size_in_kb) {
case 1: case 1:
@ -2458,491 +2460,442 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
break; break;
} }
if ((rdev->family == CHIP_TAHITI) || for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
(rdev->family == CHIP_PITCAIRN)) { tile[reg_offset] = 0;
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
switch (reg_offset) { switch(rdev->family) {
case 0: /* non-AA compressed depth or any compressed stencil */ case CHIP_TAHITI:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | case CHIP_PITCAIRN:
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | /* non-AA compressed depth or any compressed stencil */
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | NUM_BANKS(ADDR_SURF_16_BANK) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 1: /* 2xAA/4xAA compressed depth only */ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | /* 2xAA/4xAA compressed depth only */
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
case 2: /* 8xAA compressed depth only */ /* 8xAA compressed depth only */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | NUM_BANKS(ADDR_SURF_16_BANK) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
break; tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(split_equal_to_row_size) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(split_equal_to_row_size) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ TILE_SPLIT(split_equal_to_row_size) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
TILE_SPLIT(split_equal_to_row_size) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
NUM_BANKS(ADDR_SURF_16_BANK) | /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
break; TILE_SPLIT(split_equal_to_row_size) |
case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ NUM_BANKS(ADDR_SURF_16_BANK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
TILE_SPLIT(split_equal_to_row_size) | /* 1D and 1D Array Surfaces */
NUM_BANKS(ADDR_SURF_16_BANK) | tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
break; NUM_BANKS(ADDR_SURF_16_BANK) |
case 8: /* 1D and 1D Array Surfaces */ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | /* Displayable maps. */
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); NUM_BANKS(ADDR_SURF_16_BANK) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 9: /* Displayable maps. */ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | /* Display 8bpp. */
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | NUM_BANKS(ADDR_SURF_16_BANK) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 10: /* Display 8bpp. */ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | /* Display 16bpp. */
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
case 11: /* Display 16bpp. */ /* Display 32bpp. */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
break; /* Thin. */
case 12: /* Display 32bpp. */ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | NUM_BANKS(ADDR_SURF_16_BANK) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); /* Thin 8 bpp. */
break; tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 13: /* Thin. */ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | /* Thin 16 bpp. */
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 14: /* Thin 8 bpp. */ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | /* Thin 32 bpp. */
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
case 15: /* Thin 16 bpp. */ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
NUM_BANKS(ADDR_SURF_16_BANK) | /* Thin 64 bpp. */
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
break; TILE_SPLIT(split_equal_to_row_size) |
case 16: /* Thin 32 bpp. */ NUM_BANKS(ADDR_SURF_16_BANK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | /* 8 bpp PRT. */
NUM_BANKS(ADDR_SURF_16_BANK) | tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
break; NUM_BANKS(ADDR_SURF_16_BANK) |
case 17: /* Thin 64 bpp. */ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | /* 16 bpp PRT */
TILE_SPLIT(split_equal_to_row_size) | tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); NUM_BANKS(ADDR_SURF_16_BANK) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 21: /* 8 bpp PRT. */ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | /* 32 bpp PRT */
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | NUM_BANKS(ADDR_SURF_16_BANK) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
case 22: /* 16 bpp PRT */ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | /* 64 bpp PRT */
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
case 23: /* 32 bpp PRT */ /* 128 bpp PRT */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_8_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
break;
case 24: /* 64 bpp PRT */ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | break;
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | case CHIP_VERDE:
NUM_BANKS(ADDR_SURF_16_BANK) | case CHIP_OLAND:
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | case CHIP_HAINAN:
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | /* non-AA compressed depth or any compressed stencil */
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
case 25: /* 128 bpp PRT */ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
NUM_BANKS(ADDR_SURF_8_BANK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | /* 2xAA/4xAA compressed depth only */
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
default: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
gb_tile_moden = 0; NUM_BANKS(ADDR_SURF_16_BANK) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
} BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); /* 8xAA compressed depth only */
} tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
} else if ((rdev->family == CHIP_VERDE) || MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
(rdev->family == CHIP_OLAND) || PIPE_CONFIG(ADDR_SURF_P4_8x16) |
(rdev->family == CHIP_HAINAN)) { TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { NUM_BANKS(ADDR_SURF_16_BANK) |
switch (reg_offset) { BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 0: /* non-AA compressed depth or any compressed stencil */ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | NUM_BANKS(ADDR_SURF_16_BANK) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 1: /* 2xAA/4xAA compressed depth only */ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
case 2: /* 8xAA compressed depth only */ /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(split_equal_to_row_size) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | TILE_SPLIT(split_equal_to_row_size) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | NUM_BANKS(ADDR_SURF_16_BANK) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
break; tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | TILE_SPLIT(split_equal_to_row_size) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | /* 1D and 1D Array Surfaces */
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
break; MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(split_equal_to_row_size) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | /* Displayable maps. */
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
TILE_SPLIT(split_equal_to_row_size) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
NUM_BANKS(ADDR_SURF_16_BANK) | /* Display 8bpp. */
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ NUM_BANKS(ADDR_SURF_16_BANK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
TILE_SPLIT(split_equal_to_row_size) | /* Display 16bpp. */
NUM_BANKS(ADDR_SURF_16_BANK) | tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
break; NUM_BANKS(ADDR_SURF_16_BANK) |
case 8: /* 1D and 1D Array Surfaces */ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
PIPE_CONFIG(ADDR_SURF_P4_8x16) | /* Display 32bpp. */
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); NUM_BANKS(ADDR_SURF_16_BANK) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 9: /* Displayable maps. */ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | /* Thin. */
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | NUM_BANKS(ADDR_SURF_16_BANK) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
case 10: /* Display 8bpp. */ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | /* Thin 8 bpp. */
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
case 11: /* Display 16bpp. */ /* Thin 16 bpp. */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; /* Thin 32 bpp. */
case 12: /* Display 32bpp. */ tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | NUM_BANKS(ADDR_SURF_16_BANK) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); /* Thin 64 bpp. */
break; tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 13: /* Thin. */ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(split_equal_to_row_size) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | /* 8 bpp PRT. */
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 14: /* Thin 8 bpp. */ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
NUM_BANKS(ADDR_SURF_16_BANK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | /* 16 bpp PRT */
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
case 15: /* Thin 16 bpp. */ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
NUM_BANKS(ADDR_SURF_16_BANK) | /* 32 bpp PRT */
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
case 16: /* Thin 32 bpp. */ NUM_BANKS(ADDR_SURF_16_BANK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | /* 64 bpp PRT */
NUM_BANKS(ADDR_SURF_16_BANK) | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
break; NUM_BANKS(ADDR_SURF_16_BANK) |
case 17: /* Thin 64 bpp. */ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
PIPE_CONFIG(ADDR_SURF_P4_8x16) | /* 128 bpp PRT */
TILE_SPLIT(split_equal_to_row_size) | tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); NUM_BANKS(ADDR_SURF_8_BANK) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 21: /* 8 bpp PRT. */ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
NUM_BANKS(ADDR_SURF_16_BANK) | break;
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | default:
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break;
case 22: /* 16 bpp PRT */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
break;
case 23: /* 32 bpp PRT */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break;
case 24: /* 64 bpp PRT */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break;
case 25: /* 128 bpp PRT */
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_8_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
} else
DRM_ERROR("unknown asic: 0x%x\n", rdev->family); DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
}
} }
static void si_select_se_sh(struct radeon_device *rdev, static void si_select_se_sh(struct radeon_device *rdev,