clk: actions: Add gate clock support
Add support for Actions Semi gate clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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3495e29565
Коммит
103c5e1b10
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@ -1,3 +1,4 @@
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obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o
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clk-owl-y += owl-common.o
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clk-owl-y += owl-gate.o
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@ -0,0 +1,77 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL gate clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "owl-gate.h"
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void owl_gate_set(const struct owl_clk_common *common,
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const struct owl_gate_hw *gate_hw, bool enable)
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{
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int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
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u32 reg;
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set ^= enable;
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regmap_read(common->regmap, gate_hw->reg, ®);
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if (set)
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reg |= BIT(gate_hw->bit_idx);
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else
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reg &= ~BIT(gate_hw->bit_idx);
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regmap_write(common->regmap, gate_hw->reg, reg);
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}
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static void owl_gate_disable(struct clk_hw *hw)
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{
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struct owl_gate *gate = hw_to_owl_gate(hw);
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struct owl_clk_common *common = &gate->common;
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owl_gate_set(common, &gate->gate_hw, false);
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}
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static int owl_gate_enable(struct clk_hw *hw)
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{
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struct owl_gate *gate = hw_to_owl_gate(hw);
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struct owl_clk_common *common = &gate->common;
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owl_gate_set(common, &gate->gate_hw, true);
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return 0;
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}
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int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
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const struct owl_gate_hw *gate_hw)
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{
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u32 reg;
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regmap_read(common->regmap, gate_hw->reg, ®);
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if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
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reg ^= BIT(gate_hw->bit_idx);
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return !!(reg & BIT(gate_hw->bit_idx));
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}
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static int owl_gate_is_enabled(struct clk_hw *hw)
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{
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struct owl_gate *gate = hw_to_owl_gate(hw);
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struct owl_clk_common *common = &gate->common;
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return owl_gate_clk_is_enabled(common, &gate->gate_hw);
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}
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const struct clk_ops owl_gate_ops = {
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.disable = owl_gate_disable,
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.enable = owl_gate_enable,
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.is_enabled = owl_gate_is_enabled,
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};
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@ -0,0 +1,73 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL gate clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#ifndef _OWL_GATE_H_
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#define _OWL_GATE_H_
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#include "owl-common.h"
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struct owl_gate_hw {
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u32 reg;
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u8 bit_idx;
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u8 gate_flags;
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};
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struct owl_gate {
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struct owl_gate_hw gate_hw;
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struct owl_clk_common common;
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};
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#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \
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{ \
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.reg = _reg, \
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.bit_idx = _bit_idx, \
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.gate_flags = _gate_flags, \
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}
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#define OWL_GATE(_struct, _name, _parent, _reg, \
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_bit_idx, _gate_flags, _flags) \
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struct owl_gate _struct = { \
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.gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&owl_gate_ops, \
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_flags), \
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} \
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} \
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#define OWL_GATE_NO_PARENT(_struct, _name, _reg, \
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_bit_idx, _gate_flags, _flags) \
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struct owl_gate _struct = { \
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.gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
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&owl_gate_ops, \
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_flags), \
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}, \
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} \
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static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw)
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{
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struct owl_clk_common *common = hw_to_owl_clk_common(hw);
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return container_of(common, struct owl_gate, common);
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}
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void owl_gate_set(const struct owl_clk_common *common,
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const struct owl_gate_hw *gate_hw, bool enable);
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int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
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const struct owl_gate_hw *gate_hw);
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extern const struct clk_ops owl_gate_ops;
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#endif /* _OWL_GATE_H_ */
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