[MIPS] time: Add GT641xx timer0 clockevent driver
And make use of it for Cobalt. A few others such as the Malta could make use of it as well. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa
Ralf Baechle
Родитель
d04533650f
Коммит
1097c6ac33
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@ -66,6 +66,7 @@ config BCM47XX
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config MIPS_COBALT
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bool "Cobalt Server"
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select CEVT_R4K
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select CEVT_GT641XX
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select I8253
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@ -729,6 +730,9 @@ config ARCH_MAY_HAVE_PC_FDC
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config BOOT_RAW
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bool
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config CEVT_GT641XX
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bool
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config CEVT_R4K
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bool
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@ -2,7 +2,7 @@
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# Makefile for the Cobalt micro systems family specific parts of the kernel
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#
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obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o
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obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o time.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_EARLY_PRINTK) += console.o
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@ -9,19 +9,17 @@
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* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/i8253.h>
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#include <asm/io.h>
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#include <asm/reboot.h>
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#include <asm/gt64120.h>
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#include <cobalt.h>
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#include <irq.h>
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extern void cobalt_machine_restart(char *command);
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extern void cobalt_machine_halt(void);
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@ -41,17 +39,6 @@ const char *get_system_type(void)
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return "MIPS Cobalt";
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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/* Load timer value for HZ (TCLK is 50MHz) */
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GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
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/* Enable timer0 */
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GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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setup_irq(GT641XX_TIMER0_IRQ, irq);
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}
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/*
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* Cobalt doesn't have PS/2 keyboard/mouse interfaces,
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* keyboard conntroller is never used.
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@ -84,11 +71,6 @@ static struct resource cobalt_reserved_resources[] = {
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},
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};
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void __init plat_time_init(void)
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{
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setup_pit_timer();
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}
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void __init plat_mem_setup(void)
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{
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int i;
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@ -0,0 +1,35 @@
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/*
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* Cobalt time initialization.
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*
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* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <asm/gt64120.h>
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#include <asm/i8253.h>
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#include <asm/time.h>
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#define GT641XX_BASE_CLOCK 50000000 /* 50MHz */
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void __init plat_time_init(void)
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{
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setup_pit_timer();
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gt641xx_set_base_clock(GT641XX_BASE_CLOCK);
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mips_timer_state = gt641xx_timer0_state;
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}
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@ -9,6 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
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time.o topology.o traps.o unaligned.o
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obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
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obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
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irix5sys.o sysirix.o
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@ -0,0 +1,144 @@
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/*
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* GT641xx clockevent routines.
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*
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* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/gt64120.h>
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#include <asm/time.h>
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#include <irq.h>
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static DEFINE_SPINLOCK(gt641xx_timer_lock);
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static unsigned int gt641xx_base_clock;
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void gt641xx_set_base_clock(unsigned int clock)
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{
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gt641xx_base_clock = clock;
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}
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int gt641xx_timer0_state(void)
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{
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if (GT_READ(GT_TC0_OFS))
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return 0;
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GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
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GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
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return 1;
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}
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static int gt641xx_timer0_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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u32 ctrl;
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spin_lock_irqsave(>641xx_timer_lock, flags);
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ctrl = GT_READ(GT_TC_CONTROL_OFS);
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ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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ctrl |= GT_TC_CONTROL_ENTC0_MSK;
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GT_WRITE(GT_TC0_OFS, delta);
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GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
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spin_unlock_irqrestore(>641xx_timer_lock, flags);
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return 0;
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}
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static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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u32 ctrl;
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spin_lock_irqsave(>641xx_timer_lock, flags);
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ctrl = GT_READ(GT_TC_CONTROL_OFS);
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ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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ctrl |= GT_TC_CONTROL_ENTC0_MSK;
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break;
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default:
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break;
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}
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GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
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spin_unlock_irqrestore(>641xx_timer_lock, flags);
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}
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static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
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{
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}
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static struct clock_event_device gt641xx_timer0_clockevent = {
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.name = "gt641xx-timer0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.cpumask = CPU_MASK_CPU0,
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.irq = GT641XX_TIMER0_IRQ,
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.set_next_event = gt641xx_timer0_set_next_event,
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.set_mode = gt641xx_timer0_set_mode,
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.event_handler = gt641xx_timer0_event_handler,
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};
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static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd = >641xx_timer0_clockevent;
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct irqaction gt641xx_timer0_irqaction = {
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.handler = gt641xx_timer0_interrupt,
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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.name = "gt641xx_timer0",
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};
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static int __init gt641xx_timer0_clockevent_init(void)
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{
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struct clock_event_device *cd;
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if (!gt641xx_base_clock)
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return 0;
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GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
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cd = >641xx_timer0_clockevent;
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cd->rating = 200 + gt641xx_base_clock / 10000000;
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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clockevent_set_clock(cd, gt641xx_base_clock);
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clockevents_register_device(>641xx_timer0_clockevent);
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return setup_irq(GT641XX_TIMER0_IRQ, >641xx_timer0_irqaction);
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}
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arch_initcall(gt641xx_timer0_clockevent_init);
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@ -21,6 +21,8 @@
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#ifndef _ASM_GT64120_H
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#define _ASM_GT64120_H
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#include <linux/clocksource.h>
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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@ -572,4 +574,7 @@
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#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
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#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
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extern void gt641xx_set_base_clock(unsigned int clock);
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extern int gt641xx_timer0_state(void);
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#endif /* _ASM_GT64120_H */
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