[libata sata_nv] cleanups: convert #defines to enums; remove in-file history
This commit is contained in:
Jeff Garzik
Родитель
142877b07f
Коммит
10ad05df14
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@ -29,34 +29,6 @@
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* NV-specific details such as register offsets, SATA phy location,
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* NV-specific details such as register offsets, SATA phy location,
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* hotplug info, etc.
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* hotplug info, etc.
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*
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*
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* 0.10
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* - Fixed spurious interrupts issue seen with the Maxtor 6H500F0 500GB
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* drive. Also made the check_hotplug() callbacks return whether there
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* was a hotplug interrupt or not. This was not the source of the
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* spurious interrupts, but is the right thing to do anyway.
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*
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* 0.09
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* - Fixed bug introduced by 0.08's MCP51 and MCP55 support.
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*
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* 0.08
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* - Added support for MCP51 and MCP55.
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*
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* 0.07
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* - Added support for RAID class code.
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*
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* 0.06
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* - Added generic SATA support by using a pci_device_id that filters on
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* the IDE storage class code.
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*
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* 0.03
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* - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
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* mmio_base, which is only set for the CK804/MCP04 case.
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*
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* 0.02
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* - Added support for CK804 SATA controller.
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*
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* 0.01
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* - Initial revision.
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*/
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*/
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#include <linux/config.h>
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#include <linux/config.h>
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@ -74,53 +46,55 @@
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#define DRV_NAME "sata_nv"
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#define DRV_NAME "sata_nv"
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#define DRV_VERSION "0.8"
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#define DRV_VERSION "0.8"
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#define NV_PORTS 2
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enum {
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#define NV_PIO_MASK 0x1f
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NV_PORTS = 2,
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#define NV_MWDMA_MASK 0x07
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NV_PIO_MASK = 0x1f,
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#define NV_UDMA_MASK 0x7f
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NV_MWDMA_MASK = 0x07,
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#define NV_PORT0_SCR_REG_OFFSET 0x00
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NV_UDMA_MASK = 0x7f,
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#define NV_PORT1_SCR_REG_OFFSET 0x40
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NV_PORT0_SCR_REG_OFFSET = 0x00,
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NV_PORT1_SCR_REG_OFFSET = 0x40,
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#define NV_INT_STATUS 0x10
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NV_INT_STATUS = 0x10,
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#define NV_INT_STATUS_CK804 0x440
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NV_INT_STATUS_CK804 = 0x440,
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#define NV_INT_STATUS_PDEV_INT 0x01
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NV_INT_STATUS_PDEV_INT = 0x01,
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#define NV_INT_STATUS_PDEV_PM 0x02
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NV_INT_STATUS_PDEV_PM = 0x02,
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#define NV_INT_STATUS_PDEV_ADDED 0x04
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NV_INT_STATUS_PDEV_ADDED = 0x04,
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#define NV_INT_STATUS_PDEV_REMOVED 0x08
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NV_INT_STATUS_PDEV_REMOVED = 0x08,
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#define NV_INT_STATUS_SDEV_INT 0x10
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NV_INT_STATUS_SDEV_INT = 0x10,
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#define NV_INT_STATUS_SDEV_PM 0x20
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NV_INT_STATUS_SDEV_PM = 0x20,
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#define NV_INT_STATUS_SDEV_ADDED 0x40
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NV_INT_STATUS_SDEV_ADDED = 0x40,
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#define NV_INT_STATUS_SDEV_REMOVED 0x80
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NV_INT_STATUS_SDEV_REMOVED = 0x80,
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#define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
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NV_INT_STATUS_PDEV_HOTPLUG = (NV_INT_STATUS_PDEV_ADDED |
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NV_INT_STATUS_PDEV_REMOVED)
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NV_INT_STATUS_PDEV_REMOVED),
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#define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
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NV_INT_STATUS_SDEV_HOTPLUG = (NV_INT_STATUS_SDEV_ADDED |
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NV_INT_STATUS_SDEV_REMOVED)
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NV_INT_STATUS_SDEV_REMOVED),
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#define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
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NV_INT_STATUS_HOTPLUG = (NV_INT_STATUS_PDEV_HOTPLUG |
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NV_INT_STATUS_SDEV_HOTPLUG)
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NV_INT_STATUS_SDEV_HOTPLUG),
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#define NV_INT_ENABLE 0x11
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NV_INT_ENABLE = 0x11,
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#define NV_INT_ENABLE_CK804 0x441
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NV_INT_ENABLE_CK804 = 0x441,
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#define NV_INT_ENABLE_PDEV_MASK 0x01
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NV_INT_ENABLE_PDEV_MASK = 0x01,
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#define NV_INT_ENABLE_PDEV_PM 0x02
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NV_INT_ENABLE_PDEV_PM = 0x02,
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#define NV_INT_ENABLE_PDEV_ADDED 0x04
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NV_INT_ENABLE_PDEV_ADDED = 0x04,
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#define NV_INT_ENABLE_PDEV_REMOVED 0x08
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NV_INT_ENABLE_PDEV_REMOVED = 0x08,
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#define NV_INT_ENABLE_SDEV_MASK 0x10
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NV_INT_ENABLE_SDEV_MASK = 0x10,
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#define NV_INT_ENABLE_SDEV_PM 0x20
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NV_INT_ENABLE_SDEV_PM = 0x20,
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#define NV_INT_ENABLE_SDEV_ADDED 0x40
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NV_INT_ENABLE_SDEV_ADDED = 0x40,
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#define NV_INT_ENABLE_SDEV_REMOVED 0x80
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NV_INT_ENABLE_SDEV_REMOVED = 0x80,
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#define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
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NV_INT_ENABLE_PDEV_HOTPLUG = (NV_INT_ENABLE_PDEV_ADDED |
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NV_INT_ENABLE_PDEV_REMOVED)
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NV_INT_ENABLE_PDEV_REMOVED),
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#define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
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NV_INT_ENABLE_SDEV_HOTPLUG = (NV_INT_ENABLE_SDEV_ADDED |
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NV_INT_ENABLE_SDEV_REMOVED)
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NV_INT_ENABLE_SDEV_REMOVED),
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#define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
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NV_INT_ENABLE_HOTPLUG = (NV_INT_ENABLE_PDEV_HOTPLUG |
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NV_INT_ENABLE_SDEV_HOTPLUG)
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NV_INT_ENABLE_SDEV_HOTPLUG),
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#define NV_INT_CONFIG 0x12
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NV_INT_CONFIG = 0x12,
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#define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
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NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
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// For PCI config register 20
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// For PCI config register 20
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#define NV_MCP_SATA_CFG_20 0x50
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NV_MCP_SATA_CFG_20 = 0x50,
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#define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
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NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
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};
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static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static irqreturn_t nv_interrupt (int irq, void *dev_instance,
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static irqreturn_t nv_interrupt (int irq, void *dev_instance,
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