powerpc/4xx: Add check_link to struct ppc4xx_pciex_hwops
All current pcie controllers unconditionally use SDR to check the link and poll for reset. Refactor the code to include device reset in the port_init_hw() op and add a new check_link() op. This will make room fro new controllers that do not use SDR for these operations. Tested on 460ex. Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Tony Breeds
Josh Boyer
Родитель
af9719c306
Коммит
112d1fe9f7
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@ -650,12 +650,75 @@ struct ppc4xx_pciex_hwops
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int (*core_init)(struct device_node *np);
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int (*port_init_hw)(struct ppc4xx_pciex_port *port);
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int (*setup_utl)(struct ppc4xx_pciex_port *port);
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void (*check_link)(struct ppc4xx_pciex_port *port);
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};
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static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
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#ifdef CONFIG_44x
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static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
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unsigned int sdr_offset,
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unsigned int mask,
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unsigned int value,
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int timeout_ms)
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{
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u32 val;
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while(timeout_ms--) {
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val = mfdcri(SDR0, port->sdr_base + sdr_offset);
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if ((val & mask) == value) {
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pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
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port->index, sdr_offset, timeout_ms, val);
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return 0;
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}
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msleep(1);
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}
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return -1;
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}
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static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
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{
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printk(KERN_INFO "PCIE%d: Checking link...\n",
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port->index);
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/* Wait for reset to complete */
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if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
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printk(KERN_WARNING "PCIE%d: PGRST failed\n",
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port->index);
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return -1;
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}
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return 0;
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}
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static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
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{
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/* Check for card presence detect if supported, if not, just wait for
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* link unconditionally.
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*
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* note that we don't fail if there is no link, we just filter out
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* config space accesses. That way, it will be easier to implement
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* hotplug later on.
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*/
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if (!port->has_ibpre ||
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!ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
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1 << 28, 1 << 28, 100)) {
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printk(KERN_INFO
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"PCIE%d: Device detected, waiting for link...\n",
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port->index);
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if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
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0x1000, 0x1000, 2000))
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printk(KERN_WARNING
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"PCIE%d: Link up failed\n", port->index);
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else {
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printk(KERN_INFO
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"PCIE%d: link is up !\n", port->index);
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port->link = 1;
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}
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} else
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printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
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}
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/* Check various reset bits of the 440SPe PCIe core */
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static int __init ppc440spe_pciex_check_reset(struct device_node *np)
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{
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@ -806,7 +869,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
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(1 << 24) | (1 << 16), 1 << 12);
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return 0;
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return ppc4xx_pciex_port_reset_sdr(port);
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}
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static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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@ -856,6 +919,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
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.core_init = ppc440spe_pciex_core_init,
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.port_init_hw = ppc440speA_pciex_init_port_hw,
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.setup_utl = ppc440speA_pciex_init_utl,
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.check_link = ppc4xx_pciex_check_link_sdr,
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};
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static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
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@ -863,6 +927,7 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
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.core_init = ppc440spe_pciex_core_init,
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.port_init_hw = ppc440speB_pciex_init_port_hw,
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.setup_utl = ppc440speB_pciex_init_utl,
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.check_link = ppc4xx_pciex_check_link_sdr,
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};
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static int __init ppc460ex_pciex_core_init(struct device_node *np)
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@ -944,7 +1009,7 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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port->has_ibpre = 1;
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return 0;
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return ppc4xx_pciex_port_reset_sdr(port);
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}
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static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
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@ -972,6 +1037,7 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
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.core_init = ppc460ex_pciex_core_init,
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.port_init_hw = ppc460ex_pciex_init_port_hw,
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.setup_utl = ppc460ex_pciex_init_utl,
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.check_link = ppc4xx_pciex_check_link_sdr,
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};
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static int __init ppc460sx_pciex_core_init(struct device_node *np)
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@ -1075,7 +1141,7 @@ static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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port->has_ibpre = 1;
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return 0;
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return ppc4xx_pciex_port_reset_sdr(port);
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}
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static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
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@ -1089,6 +1155,7 @@ static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
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.core_init = ppc460sx_pciex_core_init,
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.port_init_hw = ppc460sx_pciex_init_port_hw,
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.setup_utl = ppc460sx_pciex_init_utl,
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.check_link = ppc4xx_pciex_check_link_sdr,
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};
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#endif /* CONFIG_44x */
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@ -1154,7 +1221,7 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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port->has_ibpre = 1;
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return 0;
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return ppc4xx_pciex_port_reset_sdr(port);
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}
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static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
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@ -1183,11 +1250,11 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
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.core_init = ppc405ex_pciex_core_init,
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.port_init_hw = ppc405ex_pciex_init_port_hw,
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.setup_utl = ppc405ex_pciex_init_utl,
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.check_link = ppc4xx_pciex_check_link_sdr,
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};
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#endif /* CONFIG_40x */
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/* Check that the core has been initied and if not, do it */
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static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
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{
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@ -1261,26 +1328,6 @@ static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port
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dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
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}
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static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
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unsigned int sdr_offset,
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unsigned int mask,
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unsigned int value,
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int timeout_ms)
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{
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u32 val;
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while(timeout_ms--) {
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val = mfdcri(SDR0, port->sdr_base + sdr_offset);
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if ((val & mask) == value) {
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pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
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port->index, sdr_offset, timeout_ms, val);
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return 0;
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}
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msleep(1);
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}
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return -1;
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}
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static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
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{
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int rc = 0;
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@ -1291,40 +1338,8 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
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if (rc != 0)
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return rc;
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printk(KERN_INFO "PCIE%d: Checking link...\n",
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port->index);
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/* Wait for reset to complete */
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if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
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printk(KERN_WARNING "PCIE%d: PGRST failed\n",
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port->index);
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return -1;
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}
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/* Check for card presence detect if supported, if not, just wait for
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* link unconditionally.
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*
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* note that we don't fail if there is no link, we just filter out
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* config space accesses. That way, it will be easier to implement
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* hotplug later on.
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*/
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if (!port->has_ibpre ||
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!ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
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1 << 28, 1 << 28, 100)) {
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printk(KERN_INFO
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"PCIE%d: Device detected, waiting for link...\n",
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port->index);
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if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
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0x1000, 0x1000, 2000))
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printk(KERN_WARNING
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"PCIE%d: Link up failed\n", port->index);
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else {
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printk(KERN_INFO
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"PCIE%d: link is up !\n", port->index);
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port->link = 1;
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}
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} else
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printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
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if (ppc4xx_pciex_hwops->check_link)
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ppc4xx_pciex_hwops->check_link(port);
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/*
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* Initialize mapping: disable all regions and configure
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@ -1347,14 +1362,17 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
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/*
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* Check for VC0 active and assert RDY.
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*/
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if (port->link &&
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ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
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1 << 16, 1 << 16, 5000)) {
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printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
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port->link = 0;
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if (port->sdr_base) {
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if (port->link &&
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ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
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1 << 16, 1 << 16, 5000)) {
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printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
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port->link = 0;
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}
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dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
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}
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dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
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msleep(100);
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return 0;
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