[SCSI] aic79xx: Sequencer update
Update sequencer code to Adaptec version 2.0.12-6.3.9. Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This commit is contained in:
Родитель
ba62cd2d01
Коммит
11668bb673
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@ -75,8 +75,7 @@ struct scb_platform_data;
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#define INITIATOR_WILDCARD (~0)
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#define SCB_LIST_NULL 0xFF00
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#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
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#define QOUTFIFO_ENTRY_VALID 0x8000
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#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000))
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#define QOUTFIFO_ENTRY_VALID 0x80
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#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
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#define SCSIID_TARGET(ahd, scsiid) \
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@ -1053,6 +1052,13 @@ typedef uint8_t ahd_mode_state;
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typedef void ahd_callback_t (void *);
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struct ahd_completion
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{
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uint16_t tag;
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uint8_t sg_status;
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uint8_t valid_tag;
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};
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struct ahd_softc {
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bus_space_tag_t tags[2];
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bus_space_handle_t bshs[2];
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@ -1142,11 +1148,11 @@ struct ahd_softc {
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struct seeprom_config *seep_config;
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/* Command Queues */
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struct ahd_completion *qoutfifo;
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uint16_t qoutfifonext;
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uint16_t qoutfifonext_valid_tag;
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uint16_t qinfifonext;
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uint16_t qinfifo[AHD_SCB_MAX];
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uint16_t *qoutfifo;
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/*
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* Our qfreeze count. The sequencer compares
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@ -39,7 +39,7 @@
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*
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* $FreeBSD$
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*/
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $"
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $"
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/*
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* This file is processed by the aic7xxx_asm utility for use in assembling
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@ -65,13 +65,6 @@ VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $"
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mvi MODE_PTR, MK_MODE(src, dst); \
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}
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#define TOGGLE_DFF_MODE \
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if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
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call toggle_dff_mode_work_around; \
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} else { \
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xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \
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}
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#define RESTORE_MODE(mode) \
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if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
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mov mode call set_mode_work_around; \
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@ -1199,7 +1192,7 @@ register TARGPCISTAT {
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/*
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* LQ Packet In
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* The last LQ Packet received
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* The last LQ Packet recieved
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*/
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register LQIN {
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address 0x020
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@ -3542,10 +3535,34 @@ scratch_ram {
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COMPLETE_DMA_SCB_HEAD {
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size 2
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}
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/* Counting semaphore to prevent new select-outs */
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/*
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* tail of list of SCBs that have
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* completed but need to be uploaded
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* to the host prior to being completed.
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*/
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COMPLETE_DMA_SCB_TAIL {
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size 2
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}
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/*
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* head of list of SCBs that have
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* been uploaded to the host, but cannot
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* be completed until the QFREEZE is in
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* full effect (i.e. no selections pending).
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*/
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COMPLETE_ON_QFREEZE_HEAD {
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size 2
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}
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/*
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* Counting semaphore to prevent new select-outs
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* The queue is frozen so long as the sequencer
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* and kernel freeze counts differ.
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*/
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QFREEZE_COUNT {
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size 2
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}
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KERNEL_QFREEZE_COUNT {
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size 2
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}
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/*
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* Mode to restore on legacy idle loop exit.
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*/
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@ -3624,6 +3641,17 @@ scratch_ram {
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QOUTFIFO_ENTRY_VALID_TAG {
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size 1
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}
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/*
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* Kernel and sequencer offsets into the queue of
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* incoming target mode command descriptors. The
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* queue is full when the KERNEL_TQINPOS == TQINPOS.
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*/
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KERNEL_TQINPOS {
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size 1
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}
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TQINPOS {
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size 1
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}
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/*
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* Base address of our shared data with the kernel driver in host
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* memory. This includes the qoutfifo and target mode
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@ -3639,17 +3667,6 @@ scratch_ram {
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QOUTFIFO_NEXT_ADDR {
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size 4
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}
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/*
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* Kernel and sequencer offsets into the queue of
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* incoming target mode command descriptors. The
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* queue is full when the KERNEL_TQINPOS == TQINPOS.
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*/
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KERNEL_TQINPOS {
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size 1
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}
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TQINPOS {
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size 1
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}
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ARG_1 {
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size 1
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mask SEND_MSG 0x80
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@ -3951,6 +3968,7 @@ const SG_PREFETCH_ADDR_MASK download
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const SG_SIZEOF download
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const PKT_OVERRUN_BUFOFFSET download
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const SCB_TRANSFER_SIZE download
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const CACHELINE_MASK download
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/*
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* BIOS SCB offsets
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@ -40,7 +40,7 @@
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* $FreeBSD$
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*/
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#99 $"
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $"
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PATCH_ARG_LIST = "struct ahd_softc *ahd"
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PREFIX = "ahd_"
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@ -68,13 +68,47 @@ no_error_set:
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}
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SET_MODE(M_SCSI, M_SCSI)
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test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
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test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz idle_loop_checkbus;
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test SEQ_FLAGS2, SELECTOUT_QFROZEN jz check_waiting_list;
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/*
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* If the kernel has caught up with us, thaw the queue.
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*/
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mov A, KERNEL_QFREEZE_COUNT;
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cmp QFREEZE_COUNT, A jne check_frozen_completions;
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mov A, KERNEL_QFREEZE_COUNT[1];
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cmp QFREEZE_COUNT[1], A jne check_frozen_completions;
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and SEQ_FLAGS2, ~SELECTOUT_QFROZEN;
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jmp check_waiting_list;
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check_frozen_completions:
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test SSTAT0, SELDO|SELINGO jnz idle_loop_checkbus;
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BEGIN_CRITICAL;
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/*
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* If we have completions stalled waiting for the qfreeze
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* to take effect, move them over to the complete_scb list
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* now that no selections are pending.
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*/
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cmp COMPLETE_ON_QFREEZE_HEAD[1],SCB_LIST_NULL je idle_loop_checkbus;
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/*
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* Find the end of the qfreeze list. The first element has
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* to be treated specially.
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*/
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bmov SCBPTR, COMPLETE_ON_QFREEZE_HEAD, 2;
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je join_lists;
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/*
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* Now the normal loop.
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*/
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bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
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join_lists:
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bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
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bmov COMPLETE_SCB_HEAD, COMPLETE_ON_QFREEZE_HEAD, 2;
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mvi COMPLETE_ON_QFREEZE_HEAD[1], SCB_LIST_NULL;
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jmp idle_loop_checkbus;
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check_waiting_list:
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cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
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/*
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* ENSELO is cleared by a SELDO, so we must test for SELDO
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* one last time.
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*/
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BEGIN_CRITICAL;
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test SSTAT0, SELDO jnz select_out;
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END_CRITICAL;
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call start_selection;
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@ -90,6 +124,13 @@ idle_loop_check_nonpackreq:
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test SSTAT2, NONPACKREQ jz . + 2;
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call unexpected_nonpkt_phase_find_ctxt;
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if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
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/*
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* On Rev A. hardware, the busy LED is only
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* turned on automaically during selections
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* and re-selections. Make the LED status
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* more useful by forcing it to be on so
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* long as one of our data FIFOs is active.
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*/
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and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
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cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
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and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
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@ -101,9 +142,9 @@ idle_loop_check_nonpackreq:
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call idle_loop_cchan;
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jmp idle_loop;
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BEGIN_CRITICAL;
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idle_loop_gsfifo:
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SET_MODE(M_SCSI, M_SCSI)
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BEGIN_CRITICAL;
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idle_loop_gsfifo_in_scsi_mode:
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test LQISTAT2, LQIGSAVAIL jz return;
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/*
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@ -152,11 +193,15 @@ END_CRITICAL;
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idle_loop_service_fifos:
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SET_MODE(M_DFF0, M_DFF0)
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BEGIN_CRITICAL;
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test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
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call longjmp;
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END_CRITICAL;
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idle_loop_next_fifo:
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SET_MODE(M_DFF1, M_DFF1)
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BEGIN_CRITICAL;
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test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
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END_CRITICAL;
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return:
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ret;
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@ -170,7 +215,6 @@ BEGIN_CRITICAL;
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test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
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test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
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test CCSCBCTL, CCSCBDONE jz return;
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END_CRITICAL;
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/* FALLTHROUGH */
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scbdma_tohost_done:
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test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
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@ -180,26 +224,18 @@ scbdma_tohost_done:
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* bad SCSI status (currently only for underruns), we
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* queue the SCB for normal completion. Otherwise, we
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* wait until any select-out activity has halted, and
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* then notify the host so that the transaction can be
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* dealt with.
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* then queue the completion.
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*/
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test SCB_SCSI_STATUS, 0xff jnz scbdma_notify_host;
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and CCSCBCTL, ~(CCARREN|CCSCBEN);
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bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . + 2;
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mvi COMPLETE_DMA_SCB_TAIL[1], SCB_LIST_NULL;
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test SCB_SCSI_STATUS, 0xff jz scbdma_queue_completion;
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bmov SCB_NEXT_COMPLETE, COMPLETE_ON_QFREEZE_HEAD, 2;
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bmov COMPLETE_ON_QFREEZE_HEAD, SCBPTR, 2 ret;
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scbdma_queue_completion:
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bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
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bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
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scbdma_notify_host:
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SET_MODE(M_SCSI, M_SCSI)
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test SCSISEQ0, ENSELO jnz return;
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test SSTAT0, (SELDO|SELINGO) jnz return;
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SET_MODE(M_CCHAN, M_CCHAN)
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/*
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* Remove SCB and notify host.
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*/
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and CCSCBCTL, ~(CCARREN|CCSCBEN);
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bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
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SET_SEQINTCODE(BAD_SCB_STATUS)
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ret;
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fill_qoutfifo_dmadone:
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and CCSCBCTL, ~(CCARREN|CCSCBEN);
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call qoutfifo_updated;
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@ -208,6 +244,7 @@ fill_qoutfifo_dmadone:
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test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
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bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
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xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
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END_CRITICAL;
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qoutfifo_updated:
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/*
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@ -324,14 +361,15 @@ fill_qoutfifo:
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* Keep track of the SCBs we are dmaing just
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* in case the DMA fails or is aborted.
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*/
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mov A, QOUTFIFO_ENTRY_VALID_TAG;
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bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
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mvi CCSCBCTL, CCSCBRESET;
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bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
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mov A, QOUTFIFO_NEXT_ADDR;
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bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
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fill_qoutfifo_loop:
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mov CCSCBRAM, SCBPTR;
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or CCSCBRAM, A, SCBPTR[1];
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bmov CCSCBRAM, SCBPTR, 2;
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mov CCSCBRAM, SCB_SGPTR[0];
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mov CCSCBRAM, QOUTFIFO_ENTRY_VALID_TAG;
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mov NONE, SDSCB_QOFF;
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inc INT_COALESCING_CMDCOUNT;
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add CMDS_PENDING, -1;
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@ -339,6 +377,18 @@ fill_qoutfifo_loop:
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
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cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
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test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
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/*
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* Don't cross an ADB or Cachline boundary when DMA'ing
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* completion entries. In PCI mode, at least in 32/33
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* configurations, the SCB DMA engine may lose its place
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* in the data-stream should the target force a retry on
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* something other than an 8byte aligned boundary. In
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* PCI-X mode, we do this to avoid split transactions since
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* many chipsets seem to be unable to format proper split
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* completions to continue the data transfer.
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*/
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add SINDEX, A, CCSCBADDR;
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test SINDEX, CACHELINE_MASK jz fill_qoutfifo_done;
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bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
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jmp fill_qoutfifo_loop;
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fill_qoutfifo_done:
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@ -354,7 +404,6 @@ dma_complete_scb:
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bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
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bmov SCBHADDR, SCB_BUSADDR, 4;
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mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
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END_CRITICAL;
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/*
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* Either post or fetch an SCB from host memory. The caller
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@ -371,9 +420,19 @@ dma_scb:
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mvi SCBHCNT, SCB_TRANSFER_SIZE;
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mov CCSCBCTL, SINDEX ret;
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BEGIN_CRITICAL;
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setjmp:
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bmov LONGJMP_ADDR, STACK, 2 ret;
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/*
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* At least on the A, a return in the same
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* instruction as the bmov results in a return
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* to the caller, not to the new address at the
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* top of the stack. Since we want the latter
|
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* (we use setjmp to register a handler from an
|
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* interrupt context but not invoke that handler
|
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* until we return to our idle loop), use a
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* separate ret instruction.
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*/
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bmov LONGJMP_ADDR, STACK, 2;
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ret;
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setjmp_inline:
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bmov LONGJMP_ADDR, STACK, 2;
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longjmp:
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@ -392,11 +451,6 @@ set_mode_work_around:
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mvi SEQINTCTL, INTVEC1DSL;
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mov MODE_PTR, SINDEX;
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clr SEQINTCTL ret;
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|
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toggle_dff_mode_work_around:
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mvi SEQINTCTL, INTVEC1DSL;
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xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
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clr SEQINTCTL ret;
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}
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@ -490,6 +544,21 @@ allocate_fifo1:
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SET_SRC_MODE M_SCSI;
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SET_DST_MODE M_SCSI;
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select_in:
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if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
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/*
|
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* On Rev A. hardware, the busy LED is only
|
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* turned on automaically during selections
|
||||
* and re-selections. Make the LED status
|
||||
* more useful by forcing it to be on from
|
||||
* the point of selection until our idle
|
||||
* loop determines that neither of our FIFOs
|
||||
* are busy. This handles the non-packetized
|
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* case nicely as we will not return to the
|
||||
* idle loop until the busfree at the end of
|
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* each transaction.
|
||||
*/
|
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or SBLKCTL, DIAGLEDEN|DIAGLEDON;
|
||||
}
|
||||
if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
|
||||
/*
|
||||
* Test to ensure that the bus has not
|
||||
|
@ -528,6 +597,21 @@ SET_SRC_MODE M_SCSI;
|
|||
SET_DST_MODE M_SCSI;
|
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select_out:
|
||||
BEGIN_CRITICAL;
|
||||
if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
|
||||
/*
|
||||
* On Rev A. hardware, the busy LED is only
|
||||
* turned on automaically during selections
|
||||
* and re-selections. Make the LED status
|
||||
* more useful by forcing it to be on from
|
||||
* the point of re-selection until our idle
|
||||
* loop determines that neither of our FIFOs
|
||||
* are busy. This handles the non-packetized
|
||||
* case nicely as we will not return to the
|
||||
* idle loop until the busfree at the end of
|
||||
* each transaction.
|
||||
*/
|
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or SBLKCTL, DIAGLEDEN|DIAGLEDON;
|
||||
}
|
||||
/* Clear out all SCBs that have been successfully sent. */
|
||||
if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
|
||||
/*
|
||||
|
@ -1000,15 +1084,9 @@ not_found_ITloop:
|
|||
/*
|
||||
* We received a "command complete" message. Put the SCB on the complete
|
||||
* queue and trigger a completion interrupt via the idle loop. Before doing
|
||||
* so, check to see if there
|
||||
* is a residual or the status byte is something other than STATUS_GOOD (0).
|
||||
* In either of these conditions, we upload the SCB back to the host so it can
|
||||
* process this information. In the case of a non zero status byte, we
|
||||
* additionally interrupt the kernel driver synchronously, allowing it to
|
||||
* decide if sense should be retrieved. If the kernel driver wishes to request
|
||||
* sense, it will fill the kernel SCB with a request sense command, requeue
|
||||
* it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
|
||||
* RETURN_1 to SEND_SENSE.
|
||||
* so, check to see if there is a residual or the status byte is something
|
||||
* other than STATUS_GOOD (0). In either of these conditions, we upload the
|
||||
* SCB back to the host so it can process this information.
|
||||
*/
|
||||
mesgin_complete:
|
||||
|
||||
|
@ -1053,6 +1131,7 @@ complete_nomsg:
|
|||
call queue_scb_completion;
|
||||
jmp await_busfree;
|
||||
|
||||
BEGIN_CRITICAL;
|
||||
freeze_queue:
|
||||
/* Cancel any pending select-out. */
|
||||
test SSTAT0, SELDO|SELINGO jnz . + 2;
|
||||
|
@ -1063,6 +1142,7 @@ freeze_queue:
|
|||
adc QFREEZE_COUNT[1], A;
|
||||
or SEQ_FLAGS2, SELECTOUT_QFROZEN;
|
||||
mov A, ACCUM_SAVE ret;
|
||||
END_CRITICAL;
|
||||
|
||||
/*
|
||||
* Complete the current FIFO's SCB if data for this same
|
||||
|
@ -1085,8 +1165,10 @@ queue_scb_completion:
|
|||
test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
|
||||
test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
|
||||
complete:
|
||||
BEGIN_CRITICAL;
|
||||
bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
|
||||
bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
|
||||
END_CRITICAL;
|
||||
bad_status:
|
||||
cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
|
||||
call freeze_queue;
|
||||
|
@ -1097,9 +1179,18 @@ upload_scb:
|
|||
* it on the host.
|
||||
*/
|
||||
bmov SCB_TAG, SCBPTR, 2;
|
||||
bmov SCB_NEXT_COMPLETE, COMPLETE_DMA_SCB_HEAD, 2;
|
||||
BEGIN_CRITICAL;
|
||||
or SCB_SGPTR, SG_STATUS_VALID;
|
||||
mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL;
|
||||
cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne add_dma_scb_tail;
|
||||
bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
|
||||
or SCB_SGPTR, SG_STATUS_VALID ret;
|
||||
bmov COMPLETE_DMA_SCB_TAIL, SCBPTR, 2 ret;
|
||||
add_dma_scb_tail:
|
||||
bmov REG0, SCBPTR, 2;
|
||||
bmov SCBPTR, COMPLETE_DMA_SCB_TAIL, 2;
|
||||
bmov SCB_NEXT_COMPLETE, REG0, 2;
|
||||
bmov COMPLETE_DMA_SCB_TAIL, REG0, 2 ret;
|
||||
END_CRITICAL;
|
||||
|
||||
/*
|
||||
* Is it a disconnect message? Set a flag in the SCB to remind us
|
||||
|
@ -1146,8 +1237,18 @@ SET_DST_MODE M_DFF1;
|
|||
await_busfree_clrchn:
|
||||
mvi DFFSXFRCTL, CLRCHN;
|
||||
await_busfree_not_m_dff:
|
||||
call clear_target_state;
|
||||
/* clear target specific flags */
|
||||
mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
|
||||
test SSTAT1,REQINIT|BUSFREE jz .;
|
||||
/*
|
||||
* We only set BUSFREE status once either a new
|
||||
* phase has been detected or we are really
|
||||
* BUSFREE. This allows the driver to know
|
||||
* that we are active on the bus even though
|
||||
* no identified transaction exists should a
|
||||
* timeout occur while awaiting busfree.
|
||||
*/
|
||||
mvi LASTPHASE, P_BUSFREE;
|
||||
test SSTAT1, BUSFREE jnz idle_loop;
|
||||
SET_SEQINTCODE(MISSED_BUSFREE)
|
||||
|
||||
|
@ -1202,11 +1303,6 @@ msgin_rdptrs_get_fifo:
|
|||
call allocate_fifo;
|
||||
jmp mesgin_done;
|
||||
|
||||
clear_target_state:
|
||||
mvi LASTPHASE, P_BUSFREE;
|
||||
/* clear target specific flags */
|
||||
mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
|
||||
|
||||
phase_lock:
|
||||
if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
|
||||
/*
|
||||
|
@ -1297,6 +1393,47 @@ service_fifo:
|
|||
/* Are we actively fetching segments? */
|
||||
test CCSGCTL, CCSGENACK jnz return;
|
||||
|
||||
/*
|
||||
* Should the other FIFO get the S/G cache first? If
|
||||
* both FIFOs have been allocated since we last checked
|
||||
* any FIFO, it is important that we service a FIFO
|
||||
* that is not actively on the bus first. This guarantees
|
||||
* that a FIFO will be freed to handle snapshot requests for
|
||||
* any FIFO that is still on the bus. Chips with RTI do not
|
||||
* perform snapshots, so don't bother with this test there.
|
||||
*/
|
||||
if ((ahd->features & AHD_RTI) == 0) {
|
||||
/*
|
||||
* If we're not still receiving SCSI data,
|
||||
* it is safe to allocate the S/G cache to
|
||||
* this FIFO.
|
||||
*/
|
||||
test DFCNTRL, SCSIEN jz idle_sgfetch_start;
|
||||
|
||||
/*
|
||||
* Switch to the other FIFO. Non-RTI chips
|
||||
* also have the "set mode" bug, so we must
|
||||
* disable interrupts during the switch.
|
||||
*/
|
||||
mvi SEQINTCTL, INTVEC1DSL;
|
||||
xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
|
||||
|
||||
/*
|
||||
* If the other FIFO needs loading, then it
|
||||
* must not have claimed the S/G cache yet
|
||||
* (SG_CACHE_AVAIL would have been cleared in
|
||||
* the orginal FIFO mode and we test this above).
|
||||
* Return to the idle loop so we can process the
|
||||
* FIFO not currently on the bus first.
|
||||
*/
|
||||
test SG_STATE, LOADING_NEEDED jz idle_sgfetch_okay;
|
||||
clr SEQINTCTL ret;
|
||||
idle_sgfetch_okay:
|
||||
xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
|
||||
clr SEQINTCTL;
|
||||
}
|
||||
|
||||
idle_sgfetch_start:
|
||||
/*
|
||||
* We fetch a "cacheline aligned" and sized amount of data
|
||||
* so we don't end up referencing a non-existant page.
|
||||
|
@ -1308,7 +1445,7 @@ service_fifo:
|
|||
mvi SGHCNT, SG_PREFETCH_CNT;
|
||||
if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
|
||||
/*
|
||||
* Need two instruction between "touches" of SGHADDR.
|
||||
* Need two instructions between "touches" of SGHADDR.
|
||||
*/
|
||||
nop;
|
||||
}
|
||||
|
@ -1658,7 +1795,7 @@ export seq_isr:
|
|||
* savepointer in the current FIFO. We do this so that
|
||||
* a pending CTXTDONE or SAVEPTR is visible in the active
|
||||
* FIFO. This status is the only way we can detect if we
|
||||
* have lost the race (e.g. host paused us) and our attepts
|
||||
* have lost the race (e.g. host paused us) and our attempts
|
||||
* to disable the channel occurred after all REQs were
|
||||
* already seen and acked (REQINIT never comes true).
|
||||
*/
|
||||
|
@ -1667,7 +1804,7 @@ export seq_isr:
|
|||
test DFCNTRL, DIRECTION jz interrupt_return;
|
||||
and DFCNTRL, ~SCSIEN;
|
||||
snapshot_wait_data_valid:
|
||||
test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz snapshot_data_valid;
|
||||
test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz interrupt_return;
|
||||
test SSTAT1, REQINIT jz snapshot_wait_data_valid;
|
||||
snapshot_data_valid:
|
||||
or DFCNTRL, SCSIEN;
|
||||
|
@ -1834,7 +1971,6 @@ pkt_saveptrs_check_status:
|
|||
dec SCB_FIFO_USE_COUNT;
|
||||
test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
|
||||
mvi DFFSXFRCTL, CLRCHN ret;
|
||||
END_CRITICAL;
|
||||
|
||||
/*
|
||||
* LAST_SEG_DONE status has been seen in the current FIFO.
|
||||
|
@ -1843,7 +1979,6 @@ END_CRITICAL;
|
|||
* Check for overrun and see if we can complete this command.
|
||||
*/
|
||||
pkt_last_seg_done:
|
||||
BEGIN_CRITICAL;
|
||||
/*
|
||||
* Mark transfer as completed.
|
||||
*/
|
||||
|
|
|
@ -37,9 +37,7 @@
|
|||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGES.
|
||||
*
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#202 $
|
||||
*
|
||||
* $FreeBSD$
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#247 $
|
||||
*/
|
||||
|
||||
#ifdef __linux__
|
||||
|
@ -332,6 +330,14 @@ ahd_restart(struct ahd_softc *ahd)
|
|||
ahd_outb(ahd, SCSISEQ1,
|
||||
ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
|
||||
ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
|
||||
|
||||
/*
|
||||
* Clear any pending sequencer interrupt. It is no
|
||||
* longer relevant since we're resetting the Program
|
||||
* Counter.
|
||||
*/
|
||||
ahd_outb(ahd, CLRINT, CLRSEQINT);
|
||||
|
||||
ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
|
||||
ahd_unpause(ahd);
|
||||
}
|
||||
|
@ -373,13 +379,7 @@ ahd_flush_qoutfifo(struct ahd_softc *ahd)
|
|||
saved_modes = ahd_save_modes(ahd);
|
||||
|
||||
/*
|
||||
* Complete any SCBs that just finished being
|
||||
* DMA'ed into the qoutfifo.
|
||||
*/
|
||||
ahd_run_qoutfifo(ahd);
|
||||
|
||||
/*
|
||||
* Flush the good status FIFO for compelted packetized commands.
|
||||
* Flush the good status FIFO for completed packetized commands.
|
||||
*/
|
||||
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
|
||||
saved_scbptr = ahd_get_scbptr(ahd);
|
||||
|
@ -400,22 +400,33 @@ ahd_flush_qoutfifo(struct ahd_softc *ahd)
|
|||
* the host before completing the command.
|
||||
*/
|
||||
fifo_mode = 0;
|
||||
rescan_fifos:
|
||||
for (i = 0; i < 2; i++) {
|
||||
/* Toggle to the other mode. */
|
||||
fifo_mode ^= 1;
|
||||
ahd_set_modes(ahd, fifo_mode, fifo_mode);
|
||||
|
||||
if (ahd_scb_active_in_fifo(ahd, scb) == 0)
|
||||
continue;
|
||||
|
||||
ahd_run_data_fifo(ahd, scb);
|
||||
|
||||
/*
|
||||
* Clearing this transaction in this FIFO may
|
||||
* cause a CFG4DATA for this same transaction
|
||||
* to assert in the other FIFO. Make sure we
|
||||
* loop one more time and check the other FIFO.
|
||||
* Running this FIFO may cause a CFG4DATA for
|
||||
* this same transaction to assert in the other
|
||||
* FIFO or a new snapshot SAVEPTRS interrupt
|
||||
* in this FIFO. Even running a FIFO may not
|
||||
* clear the transaction if we are still waiting
|
||||
* for data to drain to the host. We must loop
|
||||
* until the transaction is not active in either
|
||||
* FIFO just to be sure. Reset our loop counter
|
||||
* so we will visit both FIFOs again before
|
||||
* declaring this transaction finished. We
|
||||
* also delay a bit so that status has a chance
|
||||
* to change before we look at this FIFO again.
|
||||
*/
|
||||
i = 0;
|
||||
ahd_delay(200);
|
||||
goto rescan_fifos;
|
||||
}
|
||||
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
|
||||
ahd_set_scbptr(ahd, scbid);
|
||||
|
@ -428,19 +439,28 @@ ahd_flush_qoutfifo(struct ahd_softc *ahd)
|
|||
/*
|
||||
* The transfer completed with a residual.
|
||||
* Place this SCB on the complete DMA list
|
||||
* so that we Update our in-core copy of the
|
||||
* so that we update our in-core copy of the
|
||||
* SCB before completing the command.
|
||||
*/
|
||||
ahd_outb(ahd, SCB_SCSI_STATUS, 0);
|
||||
ahd_outb(ahd, SCB_SGPTR,
|
||||
ahd_inb_scbram(ahd, SCB_SGPTR)
|
||||
| SG_STATUS_VALID);
|
||||
ahd_outw(ahd, SCB_TAG, SCB_GET_TAG(scb));
|
||||
ahd_outw(ahd, SCB_TAG, scbid);
|
||||
ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
|
||||
comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
|
||||
ahd_outw(ahd, SCB_NEXT_COMPLETE, comp_head);
|
||||
if (SCBID_IS_NULL(comp_head))
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD,
|
||||
SCB_GET_TAG(scb));
|
||||
if (SCBID_IS_NULL(comp_head)) {
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
|
||||
} else {
|
||||
u_int tail;
|
||||
|
||||
tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
|
||||
ahd_set_scbptr(ahd, tail);
|
||||
ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
|
||||
ahd_set_scbptr(ahd, scbid);
|
||||
}
|
||||
} else
|
||||
ahd_complete_scb(ahd, scb);
|
||||
}
|
||||
|
@ -464,9 +484,22 @@ ahd_flush_qoutfifo(struct ahd_softc *ahd)
|
|||
break;
|
||||
ahd_delay(200);
|
||||
}
|
||||
if ((ccscbctl & CCSCBDIR) != 0)
|
||||
/*
|
||||
* We leave the sequencer to cleanup in the case of DMA's to
|
||||
* update the qoutfifo. In all other cases (DMA's to the
|
||||
* chip or a push of an SCB from the COMPLETE_DMA_SCB list),
|
||||
* we disable the DMA engine so that the sequencer will not
|
||||
* attempt to handle the DMA completion.
|
||||
*/
|
||||
if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
|
||||
ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
|
||||
|
||||
/*
|
||||
* Complete any SCBs that just finished
|
||||
* being DMA'ed into the qoutfifo.
|
||||
*/
|
||||
ahd_run_qoutfifo(ahd);
|
||||
|
||||
saved_scbptr = ahd_get_scbptr(ahd);
|
||||
/*
|
||||
* Manually update/complete any completed SCBs that are waiting to be
|
||||
|
@ -493,6 +526,24 @@ ahd_flush_qoutfifo(struct ahd_softc *ahd)
|
|||
scbid = next_scbid;
|
||||
}
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
|
||||
|
||||
scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
|
||||
while (!SCBID_IS_NULL(scbid)) {
|
||||
|
||||
ahd_set_scbptr(ahd, scbid);
|
||||
next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
|
||||
scb = ahd_lookup_scb(ahd, scbid);
|
||||
if (scb == NULL) {
|
||||
printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
|
||||
ahd_name(ahd), scbid);
|
||||
continue;
|
||||
}
|
||||
|
||||
ahd_complete_scb(ahd, scb);
|
||||
scbid = next_scbid;
|
||||
}
|
||||
ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
|
||||
|
||||
scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
|
||||
while (!SCBID_IS_NULL(scbid)) {
|
||||
|
@ -557,7 +608,6 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
{
|
||||
u_int seqintsrc;
|
||||
|
||||
while (1) {
|
||||
seqintsrc = ahd_inb(ahd, SEQINTSRC);
|
||||
if ((seqintsrc & CFG4DATA) != 0) {
|
||||
uint32_t datacnt;
|
||||
|
@ -611,11 +661,11 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
|
||||
if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
|
||||
/*
|
||||
* Snapshot Save Pointers. Clear
|
||||
* the snapshot and continue.
|
||||
* Snapshot Save Pointers. All that
|
||||
* is necessary to clear the snapshot
|
||||
* is a CLRCHN.
|
||||
*/
|
||||
ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
|
||||
continue;
|
||||
goto clrchn;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -630,16 +680,14 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
* Flush the data FIFO. Strickly only
|
||||
* necessary for Rev A parts.
|
||||
*/
|
||||
ahd_outb(ahd, DFCNTRL,
|
||||
ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
|
||||
ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
|
||||
|
||||
/*
|
||||
* Calculate residual.
|
||||
*/
|
||||
sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
|
||||
resid = ahd_inl(ahd, SHCNT);
|
||||
resid |=
|
||||
ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
|
||||
resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
|
||||
ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
|
||||
if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
|
||||
/*
|
||||
|
@ -675,7 +723,7 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
* done, otherwise wait for FIFOEMP.
|
||||
*/
|
||||
if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
|
||||
break;
|
||||
goto clrchn;
|
||||
} else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
|
||||
uint32_t sgptr;
|
||||
uint64_t data_addr;
|
||||
|
@ -684,7 +732,8 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
|
||||
/*
|
||||
* Disable S/G fetch so the DMA engine
|
||||
* is available to future users.
|
||||
* is available to future users. We won't
|
||||
* be using the DMA engine to load segments.
|
||||
*/
|
||||
if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
|
||||
ahd_outb(ahd, CCSGCTL, 0);
|
||||
|
@ -697,10 +746,8 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
* space in the S/G FIFO for new segments before
|
||||
* loading more segments.
|
||||
*/
|
||||
if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) == 0)
|
||||
continue;
|
||||
if ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) == 0)
|
||||
continue;
|
||||
if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
|
||||
&& (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
|
||||
|
||||
/*
|
||||
* Determine the offset of the next S/G
|
||||
|
@ -756,8 +803,8 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
dfcntrl |= SCSIENWRDIS;
|
||||
}
|
||||
ahd_outb(ahd, DFCNTRL, dfcntrl);
|
||||
} else if ((ahd_inb(ahd, SG_CACHE_SHADOW)
|
||||
& LAST_SEG_DONE) != 0) {
|
||||
}
|
||||
} else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
|
||||
|
||||
/*
|
||||
* Transfer completed to the end of SG list
|
||||
|
@ -765,12 +812,9 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
*/
|
||||
ahd_outb(ahd, SCB_SGPTR,
|
||||
ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
|
||||
break;
|
||||
goto clrchn;
|
||||
} else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
|
||||
break;
|
||||
}
|
||||
ahd_delay(200);
|
||||
}
|
||||
clrchn:
|
||||
/*
|
||||
* Clear any handler for this FIFO, decrement
|
||||
* the FIFO use count for the SCB, and release
|
||||
|
@ -781,10 +825,22 @@ ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
|
|||
ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
|
||||
ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Look for entries in the QoutFIFO that have completed.
|
||||
* The valid_tag completion field indicates the validity
|
||||
* of the entry - the valid value toggles each time through
|
||||
* the queue. We use the sg_status field in the completion
|
||||
* entry to avoid referencing the hscb if the completion
|
||||
* occurred with no errors and no residual. sg_status is
|
||||
* a copy of the first byte (little endian) of the sgptr
|
||||
* hscb field.
|
||||
*/
|
||||
void
|
||||
ahd_run_qoutfifo(struct ahd_softc *ahd)
|
||||
{
|
||||
struct ahd_completion *completion;
|
||||
struct scb *scb;
|
||||
u_int scb_index;
|
||||
|
||||
|
@ -792,11 +848,13 @@ ahd_run_qoutfifo(struct ahd_softc *ahd)
|
|||
panic("ahd_run_qoutfifo recursion");
|
||||
ahd->flags |= AHD_RUNNING_QOUTFIFO;
|
||||
ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
|
||||
while ((ahd->qoutfifo[ahd->qoutfifonext]
|
||||
& QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) {
|
||||
for (;;) {
|
||||
completion = &ahd->qoutfifo[ahd->qoutfifonext];
|
||||
|
||||
scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext]
|
||||
& ~QOUTFIFO_ENTRY_VALID_LE);
|
||||
if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
|
||||
break;
|
||||
|
||||
scb_index = ahd_le16toh(completion->tag);
|
||||
scb = ahd_lookup_scb(ahd, scb_index);
|
||||
if (scb == NULL) {
|
||||
printf("%s: WARNING no command for scb %d "
|
||||
|
@ -804,12 +862,15 @@ ahd_run_qoutfifo(struct ahd_softc *ahd)
|
|||
ahd_name(ahd), scb_index,
|
||||
ahd->qoutfifonext);
|
||||
ahd_dump_card_state(ahd);
|
||||
} else
|
||||
ahd_complete_scb(ahd, scb);
|
||||
} else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
|
||||
ahd_handle_scb_status(ahd, scb);
|
||||
} else {
|
||||
ahd_done(ahd, scb);
|
||||
}
|
||||
|
||||
ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
|
||||
if (ahd->qoutfifonext == 0)
|
||||
ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE;
|
||||
ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
|
||||
}
|
||||
ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
|
||||
}
|
||||
|
@ -875,26 +936,6 @@ ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
|
|||
ahd_name(ahd), seqintcode);
|
||||
#endif
|
||||
switch (seqintcode) {
|
||||
case BAD_SCB_STATUS:
|
||||
{
|
||||
struct scb *scb;
|
||||
u_int scbid;
|
||||
int cmds_pending;
|
||||
|
||||
scbid = ahd_get_scbptr(ahd);
|
||||
scb = ahd_lookup_scb(ahd, scbid);
|
||||
if (scb != NULL) {
|
||||
ahd_complete_scb(ahd, scb);
|
||||
} else {
|
||||
printf("%s: WARNING no command for scb %d "
|
||||
"(bad status)\n", ahd_name(ahd), scbid);
|
||||
ahd_dump_card_state(ahd);
|
||||
}
|
||||
cmds_pending = ahd_inw(ahd, CMDS_PENDING);
|
||||
if (cmds_pending > 0)
|
||||
ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1);
|
||||
break;
|
||||
}
|
||||
case ENTERING_NONPACK:
|
||||
{
|
||||
struct scb *scb;
|
||||
|
@ -1502,9 +1543,6 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
|||
&& (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
|
||||
scb = NULL;
|
||||
|
||||
/* Make sure the sequencer is in a safe location. */
|
||||
ahd_clear_critical_section(ahd);
|
||||
|
||||
if ((status0 & IOERR) != 0) {
|
||||
u_int now_lvd;
|
||||
|
||||
|
@ -1520,26 +1558,35 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
|||
ahd_setup_iocell_workaround(ahd);
|
||||
ahd_unpause(ahd);
|
||||
} else if ((status0 & OVERRUN) != 0) {
|
||||
|
||||
printf("%s: SCSI offset overrun detected. Resetting bus.\n",
|
||||
ahd_name(ahd));
|
||||
ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
|
||||
} else if ((status & SCSIRSTI) != 0) {
|
||||
|
||||
printf("%s: Someone reset channel A\n", ahd_name(ahd));
|
||||
ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
|
||||
} else if ((status & SCSIPERR) != 0) {
|
||||
|
||||
/* Make sure the sequencer is in a safe location. */
|
||||
ahd_clear_critical_section(ahd);
|
||||
|
||||
ahd_handle_transmission_error(ahd);
|
||||
} else if (lqostat0 != 0) {
|
||||
|
||||
printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
|
||||
ahd_outb(ahd, CLRLQOINT0, lqostat0);
|
||||
if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
|
||||
if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
|
||||
ahd_outb(ahd, CLRLQOINT1, 0);
|
||||
}
|
||||
} else if ((status & SELTO) != 0) {
|
||||
u_int scbid;
|
||||
|
||||
/* Stop the selection */
|
||||
ahd_outb(ahd, SCSISEQ0, 0);
|
||||
|
||||
/* Make sure the sequencer is in a safe location. */
|
||||
ahd_clear_critical_section(ahd);
|
||||
|
||||
/* No more pending messages */
|
||||
ahd_clear_msg_state(ahd);
|
||||
|
||||
|
@ -1572,24 +1619,27 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
|||
scbid);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Force a renegotiation with this target just in
|
||||
* case the cable was pulled and will later be
|
||||
* re-attached. The target may forget its negotiation
|
||||
* settings with us should it attempt to reselect
|
||||
* during the interruption. The target will not issue
|
||||
* a unit attention in this case, so we must always
|
||||
* renegotiate.
|
||||
*/
|
||||
ahd_scb_devinfo(ahd, &devinfo, scb);
|
||||
ahd_force_renegotiation(ahd, &devinfo);
|
||||
ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT);
|
||||
ahd_freeze_devq(ahd, scb);
|
||||
|
||||
/*
|
||||
* Cancel any pending transactions on the device
|
||||
* now that it seems to be missing. This will
|
||||
* also revert us to async/narrow transfers until
|
||||
* we can renegotiate with the device.
|
||||
*/
|
||||
ahd_handle_devreset(ahd, &devinfo,
|
||||
CAM_LUN_WILDCARD,
|
||||
CAM_SEL_TIMEOUT,
|
||||
"Selection Timeout",
|
||||
/*verbose_level*/1);
|
||||
}
|
||||
ahd_outb(ahd, CLRINT, CLRSCSIINT);
|
||||
ahd_iocell_first_selection(ahd);
|
||||
ahd_unpause(ahd);
|
||||
} else if ((status0 & (SELDI|SELDO)) != 0) {
|
||||
|
||||
ahd_iocell_first_selection(ahd);
|
||||
ahd_unpause(ahd);
|
||||
} else if (status3 != 0) {
|
||||
|
@ -1597,6 +1647,10 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
|||
ahd_name(ahd), status3);
|
||||
ahd_outb(ahd, CLRSINT3, status3);
|
||||
} else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
|
||||
|
||||
/* Make sure the sequencer is in a safe location. */
|
||||
ahd_clear_critical_section(ahd);
|
||||
|
||||
ahd_handle_lqiphase_error(ahd, lqistat1);
|
||||
} else if ((lqistat1 & LQICRCI_NLQ) != 0) {
|
||||
/*
|
||||
|
@ -1621,6 +1675,9 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
|||
*/
|
||||
ahd_outb(ahd, SCSISEQ0, 0);
|
||||
|
||||
/* Make sure the sequencer is in a safe location. */
|
||||
ahd_clear_critical_section(ahd);
|
||||
|
||||
/*
|
||||
* Determine what we were up to at the time of
|
||||
* the busfree.
|
||||
|
@ -1658,7 +1715,16 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
|||
clear_fifo = 0;
|
||||
packetized = (lqostat1 & LQOBUSFREE) != 0;
|
||||
if (!packetized
|
||||
&& ahd_inb(ahd, LASTPHASE) == P_BUSFREE)
|
||||
&& ahd_inb(ahd, LASTPHASE) == P_BUSFREE
|
||||
&& (ahd_inb(ahd, SSTAT0) & SELDI) == 0
|
||||
&& ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
|
||||
|| (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
|
||||
/*
|
||||
* Assume packetized if we are not
|
||||
* on the bus in a non-packetized
|
||||
* capacity and any pending selection
|
||||
* was a packetized selection.
|
||||
*/
|
||||
packetized = 1;
|
||||
break;
|
||||
}
|
||||
|
@ -3193,14 +3259,25 @@ ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
|
|||
iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
|
||||
|
||||
if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
|
||||
&& (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) {
|
||||
&& (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
|
||||
&& (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
|
||||
/*
|
||||
* Slow down our CRC interval to be
|
||||
* compatible with devices that can't
|
||||
* handle a CRC at full speed.
|
||||
* compatible with non-packetized
|
||||
* U160 devices that can't handle a
|
||||
* CRC at full speed.
|
||||
*/
|
||||
con_opts |= ENSLOWCRC;
|
||||
}
|
||||
|
||||
if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
|
||||
/*
|
||||
* On H2A4, revert to a slower slewrate
|
||||
* on non-paced transfers.
|
||||
*/
|
||||
iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
|
||||
~AHD_SLEWRATE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
|
||||
|
@ -3289,10 +3366,14 @@ ahd_update_pending_scbs(struct ahd_softc *ahd)
|
|||
* Force the sequencer to reinitialize the selection for
|
||||
* the command at the head of the execution queue if it
|
||||
* has already been setup. The negotiation changes may
|
||||
* effect whether we select-out with ATN.
|
||||
* effect whether we select-out with ATN. It is only
|
||||
* safe to clear ENSELO when the bus is not free and no
|
||||
* selection is in progres or completed.
|
||||
*/
|
||||
saved_modes = ahd_save_modes(ahd);
|
||||
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
|
||||
if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
|
||||
&& (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
|
||||
ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
|
||||
saved_scbptr = ahd_get_scbptr(ahd);
|
||||
/* Ensure that the hscbs down on the card match the new information */
|
||||
|
@ -4999,13 +5080,14 @@ ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
|
|||
ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
|
||||
AHD_TRANS_CUR, /*paused*/TRUE);
|
||||
ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
|
||||
/*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE);
|
||||
/*ppr_options*/0, AHD_TRANS_CUR,
|
||||
/*paused*/TRUE);
|
||||
|
||||
if (status != CAM_SEL_TIMEOUT)
|
||||
ahd_send_async(ahd, devinfo->channel, devinfo->target,
|
||||
lun, AC_SENT_BDR, NULL);
|
||||
CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
|
||||
|
||||
if (message != NULL
|
||||
&& (verbose_level <= bootverbose))
|
||||
if (message != NULL && bootverbose)
|
||||
printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
|
||||
message, devinfo->channel, devinfo->target, found);
|
||||
}
|
||||
|
@ -5963,16 +6045,13 @@ ahd_alloc_scbs(struct ahd_softc *ahd)
|
|||
newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
|
||||
newcount = MIN(newcount, scb_data->sgs_left);
|
||||
newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
|
||||
scb_data->sense_left -= newcount;
|
||||
scb_data->scbs_left -= newcount;
|
||||
scb_data->sgs_left -= newcount;
|
||||
for (i = 0; i < newcount; i++) {
|
||||
u_int col_tag;
|
||||
|
||||
struct scb_platform_data *pdata;
|
||||
u_int col_tag;
|
||||
#ifndef __linux__
|
||||
int error;
|
||||
#endif
|
||||
|
||||
next_scb = (struct scb *)malloc(sizeof(*next_scb),
|
||||
M_DEVBUF, M_NOWAIT);
|
||||
if (next_scb == NULL)
|
||||
|
@ -6029,6 +6108,9 @@ ahd_alloc_scbs(struct ahd_softc *ahd)
|
|||
sense_data += AHD_SENSE_BUFSIZE;
|
||||
sense_busaddr += AHD_SENSE_BUFSIZE;
|
||||
scb_data->numscbs++;
|
||||
scb_data->sense_left--;
|
||||
scb_data->scbs_left--;
|
||||
scb_data->sgs_left--;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -6143,7 +6225,7 @@ ahd_init(struct ahd_softc *ahd)
|
|||
* for the target mode role, we must additionally provide space for
|
||||
* the incoming target command fifo.
|
||||
*/
|
||||
driver_data_size = AHD_SCB_MAX * sizeof(uint16_t)
|
||||
driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
|
||||
+ sizeof(struct hardware_scb);
|
||||
if ((ahd->features & AHD_TARGETMODE) != 0)
|
||||
driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
|
||||
|
@ -6178,10 +6260,10 @@ ahd_init(struct ahd_softc *ahd)
|
|||
ahd->shared_data_map.vaddr, driver_data_size,
|
||||
ahd_dmamap_cb, &ahd->shared_data_map.physaddr,
|
||||
/*flags*/0);
|
||||
ahd->qoutfifo = (uint16_t *)ahd->shared_data_map.vaddr;
|
||||
ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
|
||||
next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
|
||||
next_baddr = ahd->shared_data_map.physaddr
|
||||
+ AHD_QOUT_SIZE*sizeof(uint16_t);
|
||||
+ AHD_QOUT_SIZE*sizeof(struct ahd_completion);
|
||||
if ((ahd->features & AHD_TARGETMODE) != 0) {
|
||||
ahd->targetcmds = (struct target_cmd *)next_vaddr;
|
||||
next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
|
||||
|
@ -6508,10 +6590,10 @@ ahd_chip_init(struct ahd_softc *ahd)
|
|||
|
||||
/* All of our queues are empty */
|
||||
ahd->qoutfifonext = 0;
|
||||
ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE;
|
||||
ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8);
|
||||
ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
|
||||
ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
|
||||
for (i = 0; i < AHD_QOUT_SIZE; i++)
|
||||
ahd->qoutfifo[i] = 0;
|
||||
ahd->qoutfifo[i].valid_tag = 0;
|
||||
ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
|
||||
|
||||
ahd->qinfifonext = 0;
|
||||
|
@ -6544,12 +6626,15 @@ ahd_chip_init(struct ahd_softc *ahd)
|
|||
ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
|
||||
ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
|
||||
ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
|
||||
ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
|
||||
|
||||
/*
|
||||
* The Freeze Count is 0.
|
||||
*/
|
||||
ahd->qfreeze_cnt = 0;
|
||||
ahd_outw(ahd, QFREEZE_COUNT, 0);
|
||||
ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
|
||||
|
||||
/*
|
||||
* Tell the sequencer where it can find our arrays in memory.
|
||||
|
@ -6909,43 +6994,34 @@ ahd_pause_and_flushwork(struct ahd_softc *ahd)
|
|||
{
|
||||
u_int intstat;
|
||||
u_int maxloops;
|
||||
u_int qfreeze_cnt;
|
||||
|
||||
maxloops = 1000;
|
||||
ahd->flags |= AHD_ALL_INTERRUPTS;
|
||||
ahd_pause(ahd);
|
||||
/*
|
||||
* Increment the QFreeze Count so that the sequencer
|
||||
* will not start new selections. We do this only
|
||||
* Freeze the outgoing selections. We do this only
|
||||
* until we are safely paused without further selections
|
||||
* pending.
|
||||
*/
|
||||
ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1);
|
||||
ahd->qfreeze_cnt--;
|
||||
ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
|
||||
ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
|
||||
do {
|
||||
struct scb *waiting_scb;
|
||||
|
||||
ahd_unpause(ahd);
|
||||
/*
|
||||
* Give the sequencer some time to service
|
||||
* any active selections.
|
||||
*/
|
||||
ahd_delay(500);
|
||||
|
||||
ahd_intr(ahd);
|
||||
ahd_pause(ahd);
|
||||
intstat = ahd_inb(ahd, INTSTAT);
|
||||
if ((intstat & INT_PEND) == 0) {
|
||||
ahd_clear_critical_section(ahd);
|
||||
intstat = ahd_inb(ahd, INTSTAT);
|
||||
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
|
||||
if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
|
||||
ahd_outb(ahd, SCSISEQ0,
|
||||
ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
|
||||
/*
|
||||
* In the non-packetized case, the sequencer (for Rev A),
|
||||
* relies on ENSELO remaining set after SELDO. The hardware
|
||||
* auto-clears ENSELO in the packetized case.
|
||||
*/
|
||||
waiting_scb = ahd_lookup_scb(ahd,
|
||||
ahd_inw(ahd, WAITING_TID_HEAD));
|
||||
if (waiting_scb != NULL
|
||||
&& (waiting_scb->flags & SCB_PACKETIZED) == 0
|
||||
&& (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)
|
||||
ahd_outb(ahd, SCSISEQ0,
|
||||
ahd_inb(ahd, SCSISEQ0) | ENSELO);
|
||||
}
|
||||
} while (--maxloops
|
||||
&& (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
|
||||
&& ((intstat & INT_PEND) != 0
|
||||
|
@ -6956,17 +7032,8 @@ ahd_pause_and_flushwork(struct ahd_softc *ahd)
|
|||
printf("Infinite interrupt loop, INTSTAT = %x",
|
||||
ahd_inb(ahd, INTSTAT));
|
||||
}
|
||||
qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT);
|
||||
if (qfreeze_cnt == 0) {
|
||||
printf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n",
|
||||
ahd_name(ahd));
|
||||
} else {
|
||||
qfreeze_cnt--;
|
||||
}
|
||||
ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt);
|
||||
if (qfreeze_cnt == 0)
|
||||
ahd_outb(ahd, SEQ_FLAGS2,
|
||||
ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN);
|
||||
ahd->qfreeze_cnt++;
|
||||
ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
|
||||
|
||||
ahd_flush_qoutfifo(ahd);
|
||||
|
||||
|
@ -7307,6 +7374,7 @@ ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
|
|||
* appropriate, traverse the SCBs of each "their id"
|
||||
* looking for matches.
|
||||
*/
|
||||
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
|
||||
savedscbptr = ahd_get_scbptr(ahd);
|
||||
tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
|
||||
tid_prev = SCB_LIST_NULL;
|
||||
|
@ -7376,7 +7444,7 @@ ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
|
|||
u_int prev;
|
||||
int found;
|
||||
|
||||
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
|
||||
AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
|
||||
found = 0;
|
||||
prev = SCB_LIST_NULL;
|
||||
next = *list_head;
|
||||
|
@ -7443,7 +7511,7 @@ static void
|
|||
ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
|
||||
u_int tid_cur, u_int tid_next)
|
||||
{
|
||||
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
|
||||
AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
|
||||
|
||||
if (SCBID_IS_NULL(tid_cur)) {
|
||||
|
||||
|
@ -7483,7 +7551,7 @@ ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
|
|||
{
|
||||
u_int tail_offset;
|
||||
|
||||
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
|
||||
AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
|
||||
if (!SCBID_IS_NULL(prev)) {
|
||||
ahd_set_scbptr(ahd, prev);
|
||||
ahd_outw(ahd, SCB_NEXT, next);
|
||||
|
@ -7888,29 +7956,34 @@ void
|
|||
ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
|
||||
{
|
||||
struct hardware_scb *hscb;
|
||||
u_int qfreeze_cnt;
|
||||
int paused;
|
||||
|
||||
/*
|
||||
* The sequencer freezes its select-out queue
|
||||
* anytime a SCSI status error occurs. We must
|
||||
* handle the error and decrement the QFREEZE count
|
||||
* to allow the sequencer to continue.
|
||||
* handle the error and increment our qfreeze count
|
||||
* to allow the sequencer to continue. We don't
|
||||
* bother clearing critical sections here since all
|
||||
* operations are on data structures that the sequencer
|
||||
* is not touching once the queue is frozen.
|
||||
*/
|
||||
hscb = scb->hscb;
|
||||
|
||||
if (ahd_is_paused(ahd)) {
|
||||
paused = 1;
|
||||
} else {
|
||||
paused = 0;
|
||||
ahd_pause(ahd);
|
||||
}
|
||||
|
||||
/* Freeze the queue until the client sees the error. */
|
||||
ahd_freeze_devq(ahd, scb);
|
||||
ahd_freeze_scb(scb);
|
||||
qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT);
|
||||
if (qfreeze_cnt == 0) {
|
||||
printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd));
|
||||
} else {
|
||||
qfreeze_cnt--;
|
||||
ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt);
|
||||
}
|
||||
if (qfreeze_cnt == 0)
|
||||
ahd_outb(ahd, SEQ_FLAGS2,
|
||||
ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN);
|
||||
ahd->qfreeze_cnt++;
|
||||
ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
|
||||
|
||||
if (paused == 0)
|
||||
ahd_unpause(ahd);
|
||||
|
||||
/* Don't want to clobber the original sense code */
|
||||
if ((scb->flags & SCB_SENSE) != 0) {
|
||||
|
@ -8323,13 +8396,14 @@ ahd_loadseq(struct ahd_softc *ahd)
|
|||
u_int sg_prefetch_cnt_limit;
|
||||
u_int sg_prefetch_align;
|
||||
u_int sg_size;
|
||||
u_int cacheline_mask;
|
||||
uint8_t download_consts[DOWNLOAD_CONST_COUNT];
|
||||
|
||||
if (bootverbose)
|
||||
printf("%s: Downloading Sequencer Program...",
|
||||
ahd_name(ahd));
|
||||
|
||||
#if DOWNLOAD_CONST_COUNT != 7
|
||||
#if DOWNLOAD_CONST_COUNT != 8
|
||||
#error "Download Const Mismatch"
|
||||
#endif
|
||||
/*
|
||||
|
@ -8365,6 +8439,9 @@ ahd_loadseq(struct ahd_softc *ahd)
|
|||
/* Round down to the nearest power of 2. */
|
||||
while (powerof2(sg_prefetch_align) == 0)
|
||||
sg_prefetch_align--;
|
||||
|
||||
cacheline_mask = sg_prefetch_align - 1;
|
||||
|
||||
/*
|
||||
* If the cacheline boundary is greater than half our prefetch RAM
|
||||
* we risk not being able to fetch even a single complete S/G
|
||||
|
@ -8405,6 +8482,7 @@ ahd_loadseq(struct ahd_softc *ahd)
|
|||
download_consts[PKT_OVERRUN_BUFOFFSET] =
|
||||
(ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
|
||||
download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
|
||||
download_consts[CACHELINE_MASK] = cacheline_mask;
|
||||
cur_patch = patches;
|
||||
downloaded = 0;
|
||||
skip_addr = 0;
|
||||
|
@ -8818,6 +8896,15 @@ ahd_dump_card_state(struct ahd_softc *ahd)
|
|||
scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
|
||||
}
|
||||
printf("\n");
|
||||
printf("Sequencer On QFreeze and Complete list: ");
|
||||
scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
|
||||
i = 0;
|
||||
while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
|
||||
ahd_set_scbptr(ahd, scb_index);
|
||||
printf("%d ", scb_index);
|
||||
scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
|
||||
}
|
||||
printf("\n");
|
||||
ahd_set_scbptr(ahd, saved_scb_index);
|
||||
dffstat = ahd_inb(ahd, DFFSTAT);
|
||||
for (i = 0; i < 2; i++) {
|
||||
|
@ -9052,7 +9139,7 @@ ahd_wait_seeprom(struct ahd_softc *ahd)
|
|||
{
|
||||
int cnt;
|
||||
|
||||
cnt = 20;
|
||||
cnt = 5000;
|
||||
while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
|
||||
ahd_delay(5);
|
||||
|
||||
|
|
|
@ -839,7 +839,7 @@ ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
|
|||
{
|
||||
ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
|
||||
/*offset*/0,
|
||||
/*len*/AHD_SCB_MAX * sizeof(uint16_t), op);
|
||||
/*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
|
@ -871,8 +871,8 @@ ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
|
|||
ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
|
||||
/*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo),
|
||||
/*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD);
|
||||
if ((ahd->qoutfifo[ahd->qoutfifonext]
|
||||
& QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag)
|
||||
if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag
|
||||
== ahd->qoutfifonext_valid_tag)
|
||||
retval |= AHD_RUN_QOUTFIFO;
|
||||
#ifdef AHD_TARGET_MODE
|
||||
if ((ahd->flags & AHD_TARGETROLE) != 0
|
||||
|
|
|
@ -1468,6 +1468,30 @@ ahd_linux_run_command(struct ahd_softc *ahd, struct ahd_linux_device *dev,
|
|||
if ((tstate->auto_negotiate & mask) != 0) {
|
||||
scb->flags |= SCB_AUTO_NEGOTIATE;
|
||||
scb->hscb->control |= MK_MESSAGE;
|
||||
} else if (cmd->cmnd[0] == INQUIRY
|
||||
&& (tinfo->curr.offset != 0
|
||||
|| tinfo->curr.width != MSG_EXT_WDTR_BUS_8_BIT
|
||||
|| tinfo->curr.ppr_options != 0)
|
||||
&& (tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)==0) {
|
||||
/*
|
||||
* The SCSI spec requires inquiry
|
||||
* commands to complete without
|
||||
* reporting unit attention conditions.
|
||||
* Because of this, an inquiry command
|
||||
* that occurs just after a device is
|
||||
* reset will result in a data phase
|
||||
* with mismatched negotiated rates.
|
||||
* The core already forces a renegotiation
|
||||
* for reset events that are visible to
|
||||
* our controller or that we initiate,
|
||||
* but a third party device reset or a
|
||||
* hot-plug insertion can still cause this
|
||||
* issue. Therefore, we force a re-negotiation
|
||||
* for every inquiry command unless we
|
||||
* are async.
|
||||
*/
|
||||
scb->flags |= SCB_NEGOTIATE;
|
||||
scb->hscb->control |= MK_MESSAGE;
|
||||
}
|
||||
|
||||
if ((dev->flags & (AHD_DEV_Q_TAGGED|AHD_DEV_Q_BASIC)) != 0) {
|
||||
|
@ -2058,6 +2082,7 @@ ahd_linux_queue_recovery_cmd(struct scsi_cmnd *cmd, scb_flag flag)
|
|||
int paused;
|
||||
int wait;
|
||||
int disconnected;
|
||||
int found;
|
||||
ahd_mode_state saved_modes;
|
||||
unsigned long flags;
|
||||
|
||||
|
@ -2176,7 +2201,8 @@ ahd_linux_queue_recovery_cmd(struct scsi_cmnd *cmd, scb_flag flag)
|
|||
last_phase = ahd_inb(ahd, LASTPHASE);
|
||||
saved_scbptr = ahd_get_scbptr(ahd);
|
||||
active_scbptr = saved_scbptr;
|
||||
if (disconnected && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0) {
|
||||
if (disconnected && ((last_phase != P_BUSFREE) ||
|
||||
(ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0)) {
|
||||
struct scb *bus_scb;
|
||||
|
||||
bus_scb = ahd_lookup_scb(ahd, active_scbptr);
|
||||
|
@ -2194,28 +2220,41 @@ ahd_linux_queue_recovery_cmd(struct scsi_cmnd *cmd, scb_flag flag)
|
|||
* bus or is in the disconnected state.
|
||||
*/
|
||||
saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
|
||||
if (last_phase != P_BUSFREE
|
||||
&& (SCB_GET_TAG(pending_scb) == active_scbptr
|
||||
if (SCB_GET_TAG(pending_scb) == active_scbptr
|
||||
|| (flag == SCB_DEVICE_RESET
|
||||
&& SCSIID_TARGET(ahd, saved_scsiid) == scmd_id(cmd)))) {
|
||||
&& SCSIID_TARGET(ahd, saved_scsiid) == scmd_id(cmd))) {
|
||||
|
||||
/*
|
||||
* We're active on the bus, so assert ATN
|
||||
* and hope that the target responds.
|
||||
*/
|
||||
pending_scb = ahd_lookup_scb(ahd, active_scbptr);
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|flag;
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET;
|
||||
ahd_outb(ahd, MSG_OUT, HOST_MSG);
|
||||
ahd_outb(ahd, SCSISIGO, last_phase|ATNO);
|
||||
scmd_printk(KERN_INFO, cmd, "Device is active, asserting ATN\n");
|
||||
scmd_printk(KERN_INFO, cmd, "BDR message in message buffer\n");
|
||||
wait = TRUE;
|
||||
} else if (last_phase != P_BUSFREE
|
||||
&& ahd_inb(ahd, SCSIPHASE) == 0) {
|
||||
/*
|
||||
* SCB is not identified, there
|
||||
* is no pending REQ, and the sequencer
|
||||
* has not seen a busfree. Looks like
|
||||
* a stuck connection waiting to
|
||||
* go busfree. Reset the bus.
|
||||
*/
|
||||
found = ahd_reset_channel(ahd, cmd->device->channel + 'A',
|
||||
/*Initiate Reset*/TRUE);
|
||||
printf("%s: Issued Channel %c Bus Reset. "
|
||||
"%d SCBs aborted\n", ahd_name(ahd),
|
||||
cmd->device->channel + 'A', found);
|
||||
} else if (disconnected) {
|
||||
|
||||
/*
|
||||
* Actually re-queue this SCB in an attempt
|
||||
* to select the device before it reconnects.
|
||||
*/
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|SCB_ABORT;
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|flag;
|
||||
ahd_set_scbptr(ahd, SCB_GET_TAG(pending_scb));
|
||||
pending_scb->hscb->cdb_len = 0;
|
||||
pending_scb->hscb->task_attribute = 0;
|
||||
|
@ -2296,12 +2335,13 @@ done:
|
|||
timer.expires = jiffies + (5 * HZ);
|
||||
timer.function = ahd_linux_sem_timeout;
|
||||
add_timer(&timer);
|
||||
printf("Recovery code sleeping\n");
|
||||
printf("%s: Recovery code sleeping\n", ahd_name(ahd));
|
||||
down(&ahd->platform_data->eh_sem);
|
||||
printf("Recovery code awake\n");
|
||||
printf("%s: Recovery code awake\n", ahd_name(ahd));
|
||||
ret = del_timer_sync(&timer);
|
||||
if (ret == 0) {
|
||||
printf("Timer Expired\n");
|
||||
printf("%s: Timer Expired (active %d)\n",
|
||||
ahd_name(ahd), dev->active);
|
||||
retval = FAILED;
|
||||
}
|
||||
}
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -2,8 +2,8 @@
|
|||
* DO NOT EDIT - This file is automatically generated
|
||||
* from the following source files:
|
||||
*
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#94 $
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#118 $
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#75 $
|
||||
*/
|
||||
|
||||
#include "aic79xx_osm.h"
|
||||
|
@ -172,21 +172,6 @@ ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x0b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
|
||||
{ "CLRSEQ_SPLTINT", 0x01, 0x01 },
|
||||
{ "CLRSEQ_PCIINT", 0x02, 0x02 },
|
||||
{ "CLRSEQ_SCSIINT", 0x04, 0x04 },
|
||||
{ "CLRSEQ_SEQINT", 0x08, 0x08 },
|
||||
{ "CLRSEQ_SWTMRTO", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT",
|
||||
0x0c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
|
||||
{ "SEQ_SPLTINT", 0x01, 0x01 },
|
||||
{ "SEQ_PCIINT", 0x02, 0x02 },
|
||||
|
@ -202,6 +187,21 @@ ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x0c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
|
||||
{ "CLRSEQ_SPLTINT", 0x01, 0x01 },
|
||||
{ "CLRSEQ_PCIINT", 0x02, 0x02 },
|
||||
{ "CLRSEQ_SCSIINT", 0x04, 0x04 },
|
||||
{ "CLRSEQ_SEQINT", 0x08, 0x08 },
|
||||
{ "CLRSEQ_SWTMRTO", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT",
|
||||
0x0c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -670,16 +670,16 @@ ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "BUSINITID",
|
||||
return (ahd_print_register(NULL, 0, "DLCOUNT",
|
||||
0x3c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DLCOUNT",
|
||||
return (ahd_print_register(NULL, 0, "BUSINITID",
|
||||
0x3c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
@ -859,21 +859,6 @@ ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x49, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
|
||||
{ "SELWIDE", 0x02, 0x02 },
|
||||
{ "ENAB20", 0x04, 0x04 },
|
||||
{ "ENAB40", 0x08, 0x08 },
|
||||
{ "DIAGLEDON", 0x40, 0x40 },
|
||||
{ "DIAGLEDEN", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL",
|
||||
0x4a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = {
|
||||
{ "AUTO_MSGOUT_DE", 0x02, 0x02 },
|
||||
{ "ENDGFORMCHK", 0x04, 0x04 },
|
||||
|
@ -891,22 +876,19 @@ ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
|
||||
{ "ARBDO", 0x01, 0x01 },
|
||||
{ "SPIORDY", 0x02, 0x02 },
|
||||
{ "OVERRUN", 0x04, 0x04 },
|
||||
{ "IOERR", 0x08, 0x08 },
|
||||
{ "SELINGO", 0x10, 0x10 },
|
||||
{ "SELDI", 0x20, 0x20 },
|
||||
{ "SELDO", 0x40, 0x40 },
|
||||
{ "TARGET", 0x80, 0x80 }
|
||||
static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
|
||||
{ "SELWIDE", 0x02, 0x02 },
|
||||
{ "ENAB20", 0x04, 0x04 },
|
||||
{ "ENAB40", 0x08, 0x08 },
|
||||
{ "DIAGLEDON", 0x40, 0x40 },
|
||||
{ "DIAGLEDEN", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
|
||||
0x4b, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL",
|
||||
0x4a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSINT0_parse_table[] = {
|
||||
|
@ -926,6 +908,24 @@ ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
|
||||
{ "ARBDO", 0x01, 0x01 },
|
||||
{ "SPIORDY", 0x02, 0x02 },
|
||||
{ "OVERRUN", 0x04, 0x04 },
|
||||
{ "IOERR", 0x08, 0x08 },
|
||||
{ "SELINGO", 0x10, 0x10 },
|
||||
{ "SELDI", 0x20, 0x20 },
|
||||
{ "SELDO", 0x40, 0x40 },
|
||||
{ "TARGET", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
|
||||
0x4b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
|
||||
{ "ENARBDO", 0x01, 0x01 },
|
||||
{ "ENSPIORDY", 0x02, 0x02 },
|
||||
|
@ -998,6 +998,19 @@ ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SIMODE2_parse_table[] = {
|
||||
{ "ENDMADONE", 0x01, 0x01 },
|
||||
{ "ENSDONE", 0x02, 0x02 },
|
||||
{ "ENWIDE_RES", 0x04, 0x04 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2",
|
||||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
|
||||
{ "CLRDMADONE", 0x01, 0x01 },
|
||||
{ "CLRSDONE", 0x02, 0x02 },
|
||||
|
@ -1012,19 +1025,6 @@ ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SIMODE2_parse_table[] = {
|
||||
{ "ENDMADONE", 0x01, 0x01 },
|
||||
{ "ENSDONE", 0x02, 0x02 },
|
||||
{ "ENWIDE_RES", 0x04, 0x04 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2",
|
||||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
|
||||
{ "DTERR", 0x01, 0x01 },
|
||||
{ "DGFORMERR", 0x02, 0x02 },
|
||||
|
@ -1220,21 +1220,6 @@ ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x53, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
|
||||
{ "ENLQOTCRC", 0x01, 0x01 },
|
||||
{ "ENLQOATNPKT", 0x02, 0x02 },
|
||||
{ "ENLQOATNLQ", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPT2", 0x08, 0x08 },
|
||||
{ "ENLQOTARGSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0",
|
||||
0x54, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
|
||||
{ "LQOTCRC", 0x01, 0x01 },
|
||||
{ "LQOATNPKT", 0x02, 0x02 },
|
||||
|
@ -1265,6 +1250,36 @@ ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x54, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
|
||||
{ "ENLQOTCRC", 0x01, 0x01 },
|
||||
{ "ENLQOATNPKT", 0x02, 0x02 },
|
||||
{ "ENLQOATNLQ", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPT2", 0x08, 0x08 },
|
||||
{ "ENLQOTARGSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0",
|
||||
0x54, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
|
||||
{ "ENLQOPHACHGINPKT", 0x01, 0x01 },
|
||||
{ "ENLQOBUSFREE", 0x02, 0x02 },
|
||||
{ "ENLQOBADQAS", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPI2", 0x08, 0x08 },
|
||||
{ "ENLQOINITSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1",
|
||||
0x55, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
|
||||
{ "LQOPHACHGINPKT", 0x01, 0x01 },
|
||||
{ "LQOBUSFREE", 0x02, 0x02 },
|
||||
|
@ -1295,21 +1310,6 @@ ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x55, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
|
||||
{ "ENLQOPHACHGINPKT", 0x01, 0x01 },
|
||||
{ "ENLQOBUSFREE", 0x02, 0x02 },
|
||||
{ "ENLQOBADQAS", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPI2", 0x08, 0x08 },
|
||||
{ "ENLQOINITSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1",
|
||||
0x55, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
|
||||
{ "LQOSTOP0", 0x01, 0x01 },
|
||||
{ "LQOPHACHGOUTPKT", 0x02, 0x02 },
|
||||
|
@ -1594,6 +1594,13 @@ ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x65, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ANNEXDAT",
|
||||
0x66, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SCSCHKN_parse_table[] = {
|
||||
{ "LSTSGCLRDIS", 0x01, 0x01 },
|
||||
{ "SHVALIDSTDIS", 0x02, 0x02 },
|
||||
|
@ -1611,13 +1618,6 @@ ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x66, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ANNEXDAT",
|
||||
0x66, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -1728,16 +1728,16 @@ ahd_pll400ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "PLL400CNT0",
|
||||
return (ahd_print_register(NULL, 0, "UNFAIRNESS",
|
||||
0x6e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "UNFAIRNESS",
|
||||
return (ahd_print_register(NULL, 0, "PLL400CNT0",
|
||||
0x6e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
@ -1787,13 +1787,6 @@ ahd_hodmaen_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x7a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SGHADDR",
|
||||
0x7c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -1802,10 +1795,10 @@ ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SGHCNT",
|
||||
0x84, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(NULL, 0, "SGHADDR",
|
||||
0x7c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
@ -1815,6 +1808,13 @@ ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x84, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SGHCNT",
|
||||
0x84, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
|
||||
{ "WR_DFTHRSH_MIN", 0x00, 0x70 },
|
||||
{ "RD_DFTHRSH_MIN", 0x00, 0x07 },
|
||||
|
@ -1950,17 +1950,6 @@ ahd_nsenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = {
|
||||
{ "CBNUM", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1",
|
||||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCRXMSG1_parse_table[] = {
|
||||
{ "CBNUM", 0xff, 0xff }
|
||||
};
|
||||
|
@ -1972,6 +1961,17 @@ ahd_cmcrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = {
|
||||
{ "CBNUM", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1",
|
||||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
@ -1983,17 +1983,6 @@ ahd_dchrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2",
|
||||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
@ -2012,6 +2001,17 @@ ahd_ost_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2",
|
||||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
@ -2023,6 +2023,17 @@ ahd_dchrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3",
|
||||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
@ -2051,17 +2062,6 @@ ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3",
|
||||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -2070,16 +2070,16 @@ ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CMCSEQBCNT",
|
||||
return (ahd_print_register(NULL, 0, "DCHSEQBCNT",
|
||||
0x94, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DCHSEQBCNT",
|
||||
return (ahd_print_register(NULL, 0, "CMCSEQBCNT",
|
||||
0x94, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
@ -2101,24 +2101,6 @@ ahd_cmcspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = {
|
||||
{ "RXSPLTRSP", 0x01, 0x01 },
|
||||
{ "RXSCEMSG", 0x02, 0x02 },
|
||||
{ "RXOVRUN", 0x04, 0x04 },
|
||||
{ "CNTNOTCMPLT", 0x08, 0x08 },
|
||||
{ "SCDATBUCKET", 0x10, 0x10 },
|
||||
{ "SCADERR", 0x20, 0x20 },
|
||||
{ "SCBCERR", 0x40, 0x40 },
|
||||
{ "STAETERM", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0",
|
||||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
|
||||
{ "RXSPLTRSP", 0x01, 0x01 },
|
||||
{ "RXSCEMSG", 0x02, 0x02 },
|
||||
|
@ -2137,15 +2119,22 @@ ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = {
|
||||
{ "RXSPLTRSP", 0x01, 0x01 },
|
||||
{ "RXSCEMSG", 0x02, 0x02 },
|
||||
{ "RXOVRUN", 0x04, 0x04 },
|
||||
{ "CNTNOTCMPLT", 0x08, 0x08 },
|
||||
{ "SCDATBUCKET", 0x10, 0x10 },
|
||||
{ "SCADERR", 0x20, 0x20 },
|
||||
{ "SCBCERR", 0x40, 0x40 },
|
||||
{ "STAETERM", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1",
|
||||
0x97, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0",
|
||||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCSPLTSTAT1_parse_table[] = {
|
||||
|
@ -2170,6 +2159,17 @@ ahd_ovlyspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x97, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1",
|
||||
0x97, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SGRXMSG0_parse_table[] = {
|
||||
{ "CFNUM", 0x07, 0x07 },
|
||||
{ "CDNUM", 0xf8, 0xf8 }
|
||||
|
@ -2320,6 +2320,17 @@ ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x9e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1",
|
||||
0x9f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SFUNCT_parse_table[] = {
|
||||
{ "TEST_NUM", 0x0f, 0x0f },
|
||||
{ "TEST_GROUP", 0xf0, 0xf0 }
|
||||
|
@ -2332,17 +2343,6 @@ ahd_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x9f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1",
|
||||
0x9f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
|
||||
{ "DPR", 0x01, 0x01 },
|
||||
{ "TWATERR", 0x02, 0x02 },
|
||||
|
@ -2537,16 +2537,16 @@ ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADDR",
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADR_BK",
|
||||
0xac, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADR_BK",
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADDR",
|
||||
0xac, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
@ -2566,22 +2566,6 @@ ahd_cmc_rambist_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
|
||||
{ "CCSGRESET", 0x01, 0x01 },
|
||||
{ "SG_FETCH_REQ", 0x02, 0x02 },
|
||||
{ "CCSGENACK", 0x08, 0x08 },
|
||||
{ "SG_CACHE_AVAIL", 0x10, 0x10 },
|
||||
{ "CCSGDONE", 0x80, 0x80 },
|
||||
{ "CCSGEN", 0x0c, 0x0c }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
|
||||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
|
||||
{ "CCSCBRESET", 0x01, 0x01 },
|
||||
{ "CCSCBDIR", 0x04, 0x04 },
|
||||
|
@ -2598,6 +2582,22 @@ ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
|
||||
{ "CCSGRESET", 0x01, 0x01 },
|
||||
{ "SG_FETCH_REQ", 0x02, 0x02 },
|
||||
{ "CCSGENACK", 0x08, 0x08 },
|
||||
{ "SG_CACHE_AVAIL", 0x10, 0x10 },
|
||||
{ "CCSGDONE", 0x80, 0x80 },
|
||||
{ "CCSGEN", 0x0c, 0x0c }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
|
||||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -2840,13 +2840,6 @@ ahd_wrtbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xc7, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DFPTRS",
|
||||
0xc8, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -2855,10 +2848,10 @@ ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DFBKPTR",
|
||||
0xc9, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(NULL, 0, "DFPTRS",
|
||||
0xc8, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
@ -2868,6 +2861,13 @@ ahd_skewcalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xc9, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DFBKPTR",
|
||||
0xc9, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DFDBCTL_parse_table[] = {
|
||||
{ "DFF_RAMBIST_EN", 0x01, 0x01 },
|
||||
{ "DFF_RAMBIST_DONE", 0x02, 0x02 },
|
||||
|
@ -3001,6 +3001,13 @@ ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xe4, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "BRKADDR0",
|
||||
0xe6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t BRKADDR1_parse_table[] = {
|
||||
{ "BRKDIS", 0x80, 0x80 }
|
||||
};
|
||||
|
@ -3012,13 +3019,6 @@ ahd_brkaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xe6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "BRKADDR0",
|
||||
0xe6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -3068,13 +3068,6 @@ ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xf2, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CURADDR",
|
||||
0xf4, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -3083,10 +3076,10 @@ ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
|
||||
0xf6, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(NULL, 0, "CURADDR",
|
||||
0xf4, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
@ -3096,6 +3089,13 @@ ahd_lastaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xf6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
|
||||
0xf6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
@ -3173,25 +3173,46 @@ ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x12c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL",
|
||||
0x12e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD",
|
||||
0x130, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
|
||||
0x12e, regvalue, cur_col, wrap));
|
||||
0x132, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT",
|
||||
0x134, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SAVED_MODE",
|
||||
0x130, regvalue, cur_col, wrap));
|
||||
0x136, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "MSG_OUT",
|
||||
0x131, regvalue, cur_col, wrap));
|
||||
0x137, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = {
|
||||
|
@ -3211,7 +3232,7 @@ int
|
|||
ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
|
||||
0x132, regvalue, cur_col, wrap));
|
||||
0x138, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
|
||||
|
@ -3230,21 +3251,21 @@ int
|
|||
ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
|
||||
0x133, regvalue, cur_col, wrap));
|
||||
0x139, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SAVED_SCSIID",
|
||||
0x134, regvalue, cur_col, wrap));
|
||||
0x13a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SAVED_LUN",
|
||||
0x135, regvalue, cur_col, wrap));
|
||||
0x13b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
|
||||
|
@ -3267,42 +3288,42 @@ int
|
|||
ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE",
|
||||
0x136, regvalue, cur_col, wrap));
|
||||
0x13c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG",
|
||||
0x137, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR",
|
||||
0x138, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR",
|
||||
0x13c, regvalue, cur_col, wrap));
|
||||
0x13d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS",
|
||||
0x140, regvalue, cur_col, wrap));
|
||||
0x13e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "TQINPOS",
|
||||
0x141, regvalue, cur_col, wrap));
|
||||
0x13f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR",
|
||||
0x140, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR",
|
||||
0x144, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t ARG_1_parse_table[] = {
|
||||
|
@ -3320,21 +3341,21 @@ int
|
|||
ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1",
|
||||
0x142, regvalue, cur_col, wrap));
|
||||
0x148, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ARG_2",
|
||||
0x143, regvalue, cur_col, wrap));
|
||||
0x149, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "LAST_MSG",
|
||||
0x144, regvalue, cur_col, wrap));
|
||||
0x14a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
|
||||
|
@ -3350,14 +3371,14 @@ int
|
|||
ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
|
||||
0x145, regvalue, cur_col, wrap));
|
||||
0x14b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INITIATOR_TAG",
|
||||
0x146, regvalue, cur_col, wrap));
|
||||
0x14c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
|
||||
|
@ -3369,63 +3390,63 @@ int
|
|||
ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2",
|
||||
0x147, regvalue, cur_col, wrap));
|
||||
0x14d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR",
|
||||
0x148, regvalue, cur_col, wrap));
|
||||
0x14e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER",
|
||||
0x14a, regvalue, cur_col, wrap));
|
||||
0x150, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS",
|
||||
0x14c, regvalue, cur_col, wrap));
|
||||
0x152, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS",
|
||||
0x14d, regvalue, cur_col, wrap));
|
||||
0x153, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CMDS_PENDING",
|
||||
0x14e, regvalue, cur_col, wrap));
|
||||
0x154, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT",
|
||||
0x150, regvalue, cur_col, wrap));
|
||||
0x156, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX",
|
||||
0x151, regvalue, cur_col, wrap));
|
||||
0x157, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE",
|
||||
0x152, regvalue, cur_col, wrap));
|
||||
0x158, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
|
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