Merge remote-tracking branch 'armsoc/at91/9x5' into at91-3.4-base2
This commit is contained in:
Nicolas Ferre
Коммит
11a25ea7e4
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@ -0,0 +1,37 @@
|
|||
/*
|
||||
* at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "at91sam9x5.dtsi"
|
||||
/include/ "at91sam9x5cm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G25-EK";
|
||||
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
|
||||
* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
|
||||
* AT91SAM9X25, AT91SAM9X35 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9x5 family SoC";
|
||||
compatible = "atmel,at91sam9x5";
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
gpio0 = &pioA;
|
||||
gpio1 = &pioB;
|
||||
gpio2 = &pioC;
|
||||
gpio3 = &pioD;
|
||||
tcb0 = &tcb0;
|
||||
tcb1 = &tcb1;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
};
|
||||
};
|
||||
|
||||
memory@20000000 {
|
||||
reg = <0x20000000 0x10000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
aic: interrupt-controller@fffff000 {
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
interrupt-parent;
|
||||
reg = <0xfffff000 0x200>;
|
||||
};
|
||||
|
||||
pit: timer@fffffe30 {
|
||||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xfffffe30 0xf>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
tcb0: timer@f8008000 {
|
||||
compatible = "atmel,at91sam9x5-tcb";
|
||||
reg = <0xf8008000 0x100>;
|
||||
interrupts = <17 4>;
|
||||
};
|
||||
|
||||
tcb1: timer@f800c000 {
|
||||
compatible = "atmel,at91sam9x5-tcb";
|
||||
reg = <0xf800c000 0x100>;
|
||||
interrupts = <17 4>;
|
||||
};
|
||||
|
||||
dma0: dma-controller@ffffec00 {
|
||||
compatible = "atmel,at91sam9g45-dma";
|
||||
reg = <0xffffec00 0x200>;
|
||||
interrupts = <20 4>;
|
||||
};
|
||||
|
||||
dma1: dma-controller@ffffee00 {
|
||||
compatible = "atmel,at91sam9g45-dma";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <21 4>;
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x100>;
|
||||
interrupts = <2 4>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x100>;
|
||||
interrupts = <2 4>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x100>;
|
||||
interrupts = <3 4>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x100>;
|
||||
interrupts = <3 4>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf801c000 0x200>;
|
||||
interrupts = <5 4>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@f8020000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8020000 0x200>;
|
||||
interrupts = <6 4>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@f8024000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8024000 0x200>;
|
||||
interrupts = <7 4>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
macb0: ethernet@f802c000 {
|
||||
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||
reg = <0xf802c000 0x100>;
|
||||
interrupts = <24 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
macb1: ethernet@f8030000 {
|
||||
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||
reg = <0xf8030000 0x100>;
|
||||
interrupts = <27 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/ {
|
||||
memory@20000000 {
|
||||
reg = <0x20000000 0x8000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -102,6 +102,15 @@ config ARCH_AT91SAM9G45
|
|||
select HAVE_AT91_DBGU1
|
||||
select AT91_SAM9G45_RESET
|
||||
|
||||
config ARCH_AT91SAM9X5
|
||||
bool "AT91SAM9x5 family"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU0
|
||||
select AT91_SAM9G45_RESET
|
||||
|
||||
config ARCH_AT91X40
|
||||
bool "AT91x40"
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
|
|||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o
|
||||
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
||||
|
||||
# AT91RM9200 board-specific support
|
||||
|
|
|
|||
|
|
@ -0,0 +1,373 @@
|
|||
/*
|
||||
* Chip-specific setup code for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2010-2012 Atmel Corporation.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/at91sam9x5.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/board.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
#include "sam9_smc.h"
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Clocks
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* The peripheral clocks.
|
||||
*/
|
||||
static struct clk pioAB_clk = {
|
||||
.name = "pioAB_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioCD_clk = {
|
||||
.name = "pioCD_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk smd_clk = {
|
||||
.name = "smd_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart0_clk = {
|
||||
.name = "usart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart1_clk = {
|
||||
.name = "usart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart2_clk = {
|
||||
.name = "usart2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* USART3 clock - Only for sam9g25/sam9x25 */
|
||||
static struct clk usart3_clk = {
|
||||
.name = "usart3_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi0_clk = {
|
||||
.name = "twi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi1_clk = {
|
||||
.name = "twi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi2_clk = {
|
||||
.name = "twi2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc0_clk = {
|
||||
.name = "mci0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi0_clk = {
|
||||
.name = "spi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi1_clk = {
|
||||
.name = "spi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart1_clk = {
|
||||
.name = "uart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tcb0_clk = {
|
||||
.name = "tcb0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pwm_clk = {
|
||||
.name = "pwm_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk adc_clk = {
|
||||
.name = "adc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk dma0_clk = {
|
||||
.name = "dma0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk dma1_clk = {
|
||||
.name = "dma1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uhphs_clk = {
|
||||
.name = "uhphs_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk udphs_clk = {
|
||||
.name = "udphs_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
|
||||
static struct clk macb0_clk = {
|
||||
.name = "pclk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
|
||||
static struct clk lcdc_clk = {
|
||||
.name = "lcdc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* isi clock - Only for sam9g25 */
|
||||
static struct clk isi_clk = {
|
||||
.name = "isi_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc1_clk = {
|
||||
.name = "mci1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* emac1 clock - Only for sam9x25 */
|
||||
static struct clk macb1_clk = {
|
||||
.name = "pclk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc_clk = {
|
||||
.name = "ssc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* can0 clock - Only for sam9x35 */
|
||||
static struct clk can0_clk = {
|
||||
.name = "can0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* can1 clock - Only for sam9x35 */
|
||||
static struct clk can1_clk = {
|
||||
.name = "can1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
|
||||
static struct clk *periph_clocks[] __initdata = {
|
||||
&pioAB_clk,
|
||||
&pioCD_clk,
|
||||
&smd_clk,
|
||||
&usart0_clk,
|
||||
&usart1_clk,
|
||||
&usart2_clk,
|
||||
&twi0_clk,
|
||||
&twi1_clk,
|
||||
&twi2_clk,
|
||||
&mmc0_clk,
|
||||
&spi0_clk,
|
||||
&spi1_clk,
|
||||
&uart0_clk,
|
||||
&uart1_clk,
|
||||
&tcb0_clk,
|
||||
&pwm_clk,
|
||||
&adc_clk,
|
||||
&dma0_clk,
|
||||
&dma1_clk,
|
||||
&uhphs_clk,
|
||||
&udphs_clk,
|
||||
&mmc1_clk,
|
||||
&ssc_clk,
|
||||
// irq0
|
||||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
/* lookup table for DT entries */
|
||||
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
|
||||
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
|
||||
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||
/* additional fake clock for macb_hclk */
|
||||
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
|
||||
};
|
||||
|
||||
/*
|
||||
* The two programmable clocks.
|
||||
* You must configure pin multiplexing to bring these signals out.
|
||||
*/
|
||||
static struct clk pck0 = {
|
||||
.name = "pck0",
|
||||
.pmc_mask = AT91_PMC_PCK0,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk pck1 = {
|
||||
.name = "pck1",
|
||||
.pmc_mask = AT91_PMC_PCK1,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static void __init at91sam9x5_register_clocks(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||
clk_register(periph_clocks[i]);
|
||||
|
||||
clkdev_add_table(periph_clocks_lookups,
|
||||
ARRAY_SIZE(periph_clocks_lookups));
|
||||
|
||||
if (cpu_is_at91sam9g25()
|
||||
|| cpu_is_at91sam9x25())
|
||||
clk_register(&usart3_clk);
|
||||
|
||||
if (cpu_is_at91sam9g25()
|
||||
|| cpu_is_at91sam9x25()
|
||||
|| cpu_is_at91sam9g35()
|
||||
|| cpu_is_at91sam9x35())
|
||||
clk_register(&macb0_clk);
|
||||
|
||||
if (cpu_is_at91sam9g15()
|
||||
|| cpu_is_at91sam9g35()
|
||||
|| cpu_is_at91sam9x35())
|
||||
clk_register(&lcdc_clk);
|
||||
|
||||
if (cpu_is_at91sam9g25())
|
||||
clk_register(&isi_clk);
|
||||
|
||||
if (cpu_is_at91sam9x25())
|
||||
clk_register(&macb1_clk);
|
||||
|
||||
if (cpu_is_at91sam9x25()
|
||||
|| cpu_is_at91sam9x35()) {
|
||||
clk_register(&can0_clk);
|
||||
clk_register(&can1_clk);
|
||||
}
|
||||
|
||||
clk_register(&pck0);
|
||||
clk_register(&pck1);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9x5 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9x5_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9x5_ioremap_registers(void)
|
||||
{
|
||||
if (of_at91sam926x_pit_init() < 0)
|
||||
panic("Impossible to find PIT\n");
|
||||
}
|
||||
|
||||
void __init at91sam9x5_initialize(void)
|
||||
{
|
||||
arm_pm_restart = at91sam9g45_restart;
|
||||
at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
|
||||
|
||||
/* Register GPIO subsystem (using DT) */
|
||||
at91_gpio_init(NULL, 0);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9x5 devices (temporary before modification of code)
|
||||
* -------------------------------------------------------------------- */
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
struct platform_device *atmel_default_console_device = NULL;
|
||||
|
||||
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Interrupt initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
||||
*/
|
||||
static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
||||
7, /* Advanced Interrupt Controller (FIQ) */
|
||||
7, /* System Peripherals */
|
||||
1, /* Parallel IO Controller A and B */
|
||||
1, /* Parallel IO Controller C and D */
|
||||
4, /* Soft Modem */
|
||||
5, /* USART 0 */
|
||||
5, /* USART 1 */
|
||||
5, /* USART 2 */
|
||||
5, /* USART 3 */
|
||||
6, /* Two-Wire Interface 0 */
|
||||
6, /* Two-Wire Interface 1 */
|
||||
6, /* Two-Wire Interface 2 */
|
||||
0, /* Multimedia Card Interface 0 */
|
||||
5, /* Serial Peripheral Interface 0 */
|
||||
5, /* Serial Peripheral Interface 1 */
|
||||
5, /* UART 0 */
|
||||
5, /* UART 1 */
|
||||
0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
0, /* Pulse Width Modulation Controller */
|
||||
0, /* ADC Controller */
|
||||
0, /* DMA Controller 0 */
|
||||
0, /* DMA Controller 1 */
|
||||
2, /* USB Host High Speed port */
|
||||
2, /* USB Device High speed port */
|
||||
3, /* Ethernet MAC 0 */
|
||||
3, /* LDC Controller or Image Sensor Interface */
|
||||
0, /* Multimedia Card Interface 1 */
|
||||
3, /* Ethernet MAC 1 */
|
||||
4, /* Synchronous Serial Interface */
|
||||
4, /* CAN Controller 0 */
|
||||
4, /* CAN Controller 1 */
|
||||
0, /* Advanced Interrupt Controller (IRQ0) */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91sam9x5_soc = {
|
||||
.map_io = at91sam9x5_map_io,
|
||||
.default_irq_priority = at91sam9x5_default_irq_priority,
|
||||
.ioremap_registers = at91sam9x5_ioremap_registers,
|
||||
.register_clocks = at91sam9x5_register_clocks,
|
||||
.init = at91sam9x5_initialize,
|
||||
};
|
||||
|
|
@ -109,6 +109,7 @@ static void __init at91_dt_device_init(void)
|
|||
|
||||
static const char *at91_dt_board_compat[] __initdata = {
|
||||
"atmel,at91sam9m10g45ek",
|
||||
"atmel,at91sam9x5ek",
|
||||
"calao,usb-a9g20",
|
||||
NULL
|
||||
};
|
||||
|
|
|
|||
|
|
@ -48,24 +48,37 @@
|
|||
* Chips have some kind of clocks : group them by functionality
|
||||
*/
|
||||
#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45())
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
||||
|| cpu_is_at91sam9g45())
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||
|
||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45()))
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|
||||
#define cpu_has_upll() (cpu_is_at91sam9g45())
|
||||
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
/* USB host HS & FS */
|
||||
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
|
||||
|
||||
/* USB device FS only */
|
||||
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45()))
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|
||||
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
|
||||
|
||||
static LIST_HEAD(clocks);
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
|
@ -138,13 +151,6 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
|
|||
{
|
||||
unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
|
||||
|
||||
if (cpu_is_at91sam9g45()) {
|
||||
if (is_on)
|
||||
uckr |= AT91_PMC_BIASEN;
|
||||
else
|
||||
uckr &= ~AT91_PMC_BIASEN;
|
||||
}
|
||||
|
||||
if (is_on) {
|
||||
is_on = AT91_PMC_LOCKU;
|
||||
at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
|
||||
|
|
@ -209,11 +215,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
|
|||
return &utmi_clk;
|
||||
else if (cpu_has_pllb())
|
||||
return &pllb;
|
||||
break;
|
||||
/* alternate PMC: can use master clock */
|
||||
case AT91_PMC_CSS_MASTER:
|
||||
return &mck;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int pmc_prescaler_divider(u32 reg)
|
||||
{
|
||||
if (cpu_has_alt_prescaler()) {
|
||||
return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
|
||||
} else {
|
||||
return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
static void __clk_enable(struct clk *clk)
|
||||
{
|
||||
if (clk->parent)
|
||||
|
|
@ -315,12 +334,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
|||
{
|
||||
unsigned long flags;
|
||||
unsigned prescale;
|
||||
unsigned long prescale_offset, css_mask;
|
||||
unsigned long actual;
|
||||
|
||||
if (!clk_is_programmable(clk))
|
||||
return -EINVAL;
|
||||
if (clk->users)
|
||||
return -EBUSY;
|
||||
|
||||
if (cpu_has_alt_prescaler()) {
|
||||
prescale_offset = PMC_ALT_PRES_OFFSET;
|
||||
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||
} else {
|
||||
prescale_offset = PMC_PRES_OFFSET;
|
||||
css_mask = AT91_PMC_CSS;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
|
||||
actual = clk->parent->rate_hz;
|
||||
|
|
@ -329,8 +358,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
|||
u32 pckr;
|
||||
|
||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
||||
pckr &= AT91_PMC_CSS; /* clock selection */
|
||||
pckr |= prescale << 2;
|
||||
pckr &= css_mask; /* keep clock selection */
|
||||
pckr |= prescale << prescale_offset;
|
||||
at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
|
||||
clk->rate_hz = actual;
|
||||
break;
|
||||
|
|
@ -377,11 +406,17 @@ static void __init init_programmable_clock(struct clk *clk)
|
|||
{
|
||||
struct clk *parent;
|
||||
u32 pckr;
|
||||
unsigned int css_mask;
|
||||
|
||||
if (cpu_has_alt_prescaler())
|
||||
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||
else
|
||||
css_mask = AT91_PMC_CSS;
|
||||
|
||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
||||
parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
|
||||
parent = at91_css_to_clk(pckr & css_mask);
|
||||
clk->parent = parent;
|
||||
clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
|
||||
clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
|
||||
|
|
@ -663,7 +698,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
if (pll_overclock)
|
||||
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
||||
|
||||
if (cpu_is_at91sam9g45()) {
|
||||
if (cpu_has_plladiv2()) {
|
||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
||||
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
|
||||
}
|
||||
|
|
@ -685,6 +720,10 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
||||
*/
|
||||
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
||||
|
||||
/* UTMI bias and PLL are managed at the same time */
|
||||
if (cpu_has_upll())
|
||||
utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -703,7 +742,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
||||
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
||||
freq = mck.parent->rate_hz;
|
||||
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
|
||||
freq /= pmc_prescaler_divider(mckr); /* prescale */
|
||||
if (cpu_is_at91rm9200()) {
|
||||
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
} else if (cpu_is_at91sam9g20()) {
|
||||
|
|
@ -711,13 +750,19 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
||||
if (mckr & AT91_PMC_PDIV)
|
||||
freq /= 2; /* processor clock division */
|
||||
} else if (cpu_is_at91sam9g45()) {
|
||||
} else if (cpu_has_mdiv3()) {
|
||||
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
||||
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
} else {
|
||||
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
}
|
||||
|
||||
if (cpu_has_alt_prescaler()) {
|
||||
/* Programmable clocks can use MCK */
|
||||
mck.type |= CLK_TYPE_PRIMARY;
|
||||
mck.id = 4;
|
||||
}
|
||||
|
||||
/* Register the PMC's standard clocks */
|
||||
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
||||
at91_clk_add(standard_pmc_clocks[i]);
|
||||
|
|
|
|||
|
|
@ -45,9 +45,13 @@
|
|||
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
||||
|
||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
|
||||
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
|
||||
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
|
||||
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
|
||||
|
||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||
|
|
@ -72,14 +76,24 @@
|
|||
#define AT91_PMC_CSS_PLLA (2 << 0)
|
||||
#define AT91_PMC_CSS_PLLB (3 << 0)
|
||||
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
||||
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
|
||||
#define AT91_PMC_PRES_1 (0 << 2)
|
||||
#define AT91_PMC_PRES_2 (1 << 2)
|
||||
#define AT91_PMC_PRES_4 (2 << 2)
|
||||
#define AT91_PMC_PRES_8 (3 << 2)
|
||||
#define AT91_PMC_PRES_16 (4 << 2)
|
||||
#define AT91_PMC_PRES_32 (5 << 2)
|
||||
#define AT91_PMC_PRES_64 (6 << 2)
|
||||
#define PMC_PRES_OFFSET 2
|
||||
#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
|
||||
#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
|
||||
#define PMC_ALT_PRES_OFFSET 4
|
||||
#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
|
||||
#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
||||
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
||||
|
|
@ -103,7 +117,14 @@
|
|||
#define AT91_PMC_USBS_UPLL (1 << 0)
|
||||
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
||||
|
||||
#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */
|
||||
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
|
||||
#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
|
||||
#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||
#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
|
||||
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
|
||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
||||
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
||||
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
||||
|
|
@ -120,10 +141,25 @@
|
|||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
|
||||
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
|
||||
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
|
||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */
|
||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
||||
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
|
||||
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
|
||||
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
|
||||
|
||||
#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */
|
||||
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
|
||||
|
||||
#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */
|
||||
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
|
||||
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
|
||||
#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
|
||||
#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV)
|
||||
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Chip-specific header file for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9x5 datasheet.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9X5_H
|
||||
#define AT91SAM9X5_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
|
||||
#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
|
||||
#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
|
||||
#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
|
||||
#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
|
||||
#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
|
||||
#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
|
||||
#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
|
||||
#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
|
||||
#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
|
||||
#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
|
||||
#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
|
||||
#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
|
||||
#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
|
||||
#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
|
||||
#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
|
||||
#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
|
||||
#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
|
||||
#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
|
||||
#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
|
||||
#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
|
||||
#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9X5_BASE_USART0 0xf801c000
|
||||
#define AT91SAM9X5_BASE_USART1 0xf8020000
|
||||
#define AT91SAM9X5_BASE_USART2 0xf8024000
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
|
||||
/*
|
||||
* Base addresses for early serial code (uncompress.h)
|
||||
*/
|
||||
#define AT91_DBGU AT91_BASE_DBGU0
|
||||
#define AT91_USART0 AT91SAM9X5_BASE_USART0
|
||||
#define AT91_USART1 AT91SAM9X5_BASE_USART1
|
||||
#define AT91_USART2 AT91SAM9X5_BASE_USART2
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Matrix-centric header file for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9X5_MATRIX_H
|
||||
#define AT91SAM9X5_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
|
|
@ -34,6 +34,8 @@
|
|||
#include <mach/at91sam9rl.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#include <mach/at91sam9g45.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9X5)
|
||||
#include <mach/at91sam9x5.h>
|
||||
#elif defined(CONFIG_ARCH_AT91X40)
|
||||
#include <mach/at91x40.h>
|
||||
#else
|
||||
|
|
|
|||
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