[PATCH] x86_64: Some housekeeping in local APIC code
Remove support for obsolete hardware and cleanup. - Remove checks for non integrated APICs - Replace apic_write_around with apic_write. - Remove apic_read_around - Remove APIC version reads used by old workarounds - Remove old workaround for Simics - Fix indentation Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Andi Kleen
Linus Torvalds
Родитель
5f1d189f8a
Коммит
11a8e778c4
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@ -53,20 +53,17 @@ static void apic_pm_activate(void);
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void enable_NMI_through_LVT0 (void * dummy)
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{
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unsigned int v, ver;
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unsigned int v;
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ver = apic_read(APIC_LVR);
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ver = GET_APIC_VERSION(ver);
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v = APIC_DM_NMI; /* unmask and set to NMI */
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apic_write_around(APIC_LVT0, v);
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apic_write(APIC_LVT0, v);
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}
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int get_maxlvt(void)
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{
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unsigned int v, ver, maxlvt;
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unsigned int v, maxlvt;
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v = apic_read(APIC_LVR);
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ver = GET_APIC_VERSION(v);
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maxlvt = GET_APIC_MAXLVT(v);
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return maxlvt;
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}
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@ -84,33 +81,33 @@ void clear_local_APIC(void)
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*/
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if (maxlvt >= 3) {
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v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
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apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
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apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
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}
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/*
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* Careful: we have to set masks only first to deassert
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* any level-triggered sources.
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*/
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v = apic_read(APIC_LVTT);
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apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
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apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
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v = apic_read(APIC_LVT0);
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apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
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apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
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v = apic_read(APIC_LVT1);
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apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
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apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
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if (maxlvt >= 4) {
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v = apic_read(APIC_LVTPC);
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apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
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apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
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}
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/*
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* Clean APIC state for other OSs:
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*/
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apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
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apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
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apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
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apic_write(APIC_LVTT, APIC_LVT_MASKED);
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apic_write(APIC_LVT0, APIC_LVT_MASKED);
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apic_write(APIC_LVT1, APIC_LVT_MASKED);
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if (maxlvt >= 3)
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apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
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apic_write(APIC_LVTERR, APIC_LVT_MASKED);
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if (maxlvt >= 4)
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apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
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apic_write(APIC_LVTPC, APIC_LVT_MASKED);
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v = GET_APIC_VERSION(apic_read(APIC_LVR));
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apic_write(APIC_ESR, 0);
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apic_read(APIC_ESR);
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@ -155,7 +152,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
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value &= ~APIC_VECTOR_MASK;
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value |= APIC_SPIV_APIC_ENABLED;
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value |= 0xf;
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apic_write_around(APIC_SPIV, value);
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apic_write(APIC_SPIV, value);
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if (!virt_wire_setup) {
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/* For LVT0 make it edge triggered, active high, external and enabled */
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@ -165,11 +162,11 @@ void disconnect_bsp_APIC(int virt_wire_setup)
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APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
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value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
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value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
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apic_write_around(APIC_LVT0, value);
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apic_write(APIC_LVT0, value);
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}
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else {
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/* Disable LVT0 */
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apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
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apic_write(APIC_LVT0, APIC_LVT_MASKED);
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}
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/* For LVT1 make it edge triggered, active high, nmi and enabled */
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@ -180,7 +177,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
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APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
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value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
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value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
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apic_write_around(APIC_LVT1, value);
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apic_write(APIC_LVT1, value);
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}
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}
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@ -196,7 +193,7 @@ void disable_local_APIC(void)
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*/
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value = apic_read(APIC_SPIV);
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value &= ~APIC_SPIV_APIC_ENABLED;
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apic_write_around(APIC_SPIV, value);
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apic_write(APIC_SPIV, value);
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}
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/*
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@ -273,7 +270,7 @@ void __init sync_Arb_IDs(void)
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apic_wait_icr_idle();
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apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
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apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
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apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
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| APIC_DM_INIT);
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}
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@ -284,7 +281,7 @@ extern void __error_in_apic_c (void);
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*/
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void __init init_bsp_APIC(void)
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{
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unsigned int value, ver;
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unsigned int value;
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/*
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* Don't do the setup now if we have a SMP BIOS as the
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@ -294,7 +291,6 @@ void __init init_bsp_APIC(void)
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return;
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value = apic_read(APIC_LVR);
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ver = GET_APIC_VERSION(value);
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/*
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* Do not trust the local APIC being empty at bootup.
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@ -309,22 +305,21 @@ void __init init_bsp_APIC(void)
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value |= APIC_SPIV_APIC_ENABLED;
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value |= APIC_SPIV_FOCUS_DISABLED;
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value |= SPURIOUS_APIC_VECTOR;
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apic_write_around(APIC_SPIV, value);
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apic_write(APIC_SPIV, value);
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/*
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* Set up the virtual wire mode.
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*/
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apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
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apic_write(APIC_LVT0, APIC_DM_EXTINT);
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value = APIC_DM_NMI;
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apic_write_around(APIC_LVT1, value);
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apic_write(APIC_LVT1, value);
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}
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void __cpuinit setup_local_APIC (void)
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{
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unsigned int value, ver, maxlvt;
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unsigned int value, maxlvt;
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value = apic_read(APIC_LVR);
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ver = GET_APIC_VERSION(value);
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if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
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__error_in_apic_c();
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@ -349,7 +344,7 @@ void __cpuinit setup_local_APIC (void)
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*/
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value = apic_read(APIC_TASKPRI);
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value &= ~APIC_TPRI_MASK;
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apic_write_around(APIC_TASKPRI, value);
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apic_write(APIC_TASKPRI, value);
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/*
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* Now that we are all set up, enable the APIC
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@ -391,7 +386,7 @@ void __cpuinit setup_local_APIC (void)
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* Set spurious IRQ vector
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*/
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value |= SPURIOUS_APIC_VECTOR;
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apic_write_around(APIC_SPIV, value);
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apic_write(APIC_SPIV, value);
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/*
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* Set up LVT0, LVT1:
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@ -411,7 +406,7 @@ void __cpuinit setup_local_APIC (void)
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value = APIC_DM_EXTINT | APIC_LVT_MASKED;
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apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
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}
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apic_write_around(APIC_LVT0, value);
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apic_write(APIC_LVT0, value);
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/*
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* only the BP should see the LINT1 NMI signal, obviously.
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@ -420,14 +415,14 @@ void __cpuinit setup_local_APIC (void)
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value = APIC_DM_NMI;
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else
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value = APIC_DM_NMI | APIC_LVT_MASKED;
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apic_write_around(APIC_LVT1, value);
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apic_write(APIC_LVT1, value);
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{
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unsigned oldvalue;
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maxlvt = get_maxlvt();
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oldvalue = apic_read(APIC_ESR);
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value = ERROR_APIC_VECTOR; // enables sending errors
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apic_write_around(APIC_LVTERR, value);
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apic_write(APIC_LVTERR, value);
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/*
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* spec says clear errors after enabling vector.
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*/
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@ -672,17 +667,17 @@ static void __setup_APIC_LVTT(unsigned int clocks)
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if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask))
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lvtt_value |= APIC_LVT_MASKED;
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apic_write_around(APIC_LVTT, lvtt_value);
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apic_write(APIC_LVTT, lvtt_value);
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/*
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* Divide PICLK by 16
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*/
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tmp_value = apic_read(APIC_TDCR);
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apic_write_around(APIC_TDCR, (tmp_value
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apic_write(APIC_TDCR, (tmp_value
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& ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
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| APIC_TDR_DIV_16);
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apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
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apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
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}
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static void setup_APIC_timer(unsigned int clocks)
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@ -691,12 +686,6 @@ static void setup_APIC_timer(unsigned int clocks)
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local_irq_save(flags);
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/* For some reasons this doesn't work on Simics, so fake it for now */
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if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) {
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__setup_APIC_LVTT(clocks);
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return;
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}
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/* wait for irq slice */
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if (vxtime.hpet_address) {
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int trigger = hpet_readl(HPET_T0_CMP);
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@ -709,7 +698,7 @@ static void setup_APIC_timer(unsigned int clocks)
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outb_p(0x00, 0x43);
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c2 = inb_p(0x40);
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c2 |= inb_p(0x40) << 8;
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do {
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do {
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c1 = c2;
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outb_p(0x00, 0x43);
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c2 = inb_p(0x40);
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@ -800,7 +789,7 @@ void disable_APIC_timer(void)
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unsigned long v;
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v = apic_read(APIC_LVTT);
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apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
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apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
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}
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}
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@ -813,7 +802,7 @@ void enable_APIC_timer(void)
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unsigned long v;
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v = apic_read(APIC_LVTT);
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apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
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apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED);
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}
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}
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@ -1066,7 +1055,7 @@ int __init APIC_init_uniprocessor (void)
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connect_bsp_APIC();
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phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
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apic_write_around(APIC_ID, SET_APIC_ID(boot_cpu_id));
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apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
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setup_local_APIC();
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@ -910,7 +910,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
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disable_8259A_irq(0);
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/* mask LVT0 */
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apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
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apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
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/*
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* We use logical delivery to get the timer IRQ
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@ -1635,7 +1635,7 @@ static void enable_lapic_irq (unsigned int irq)
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unsigned long v;
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v = apic_read(APIC_LVT0);
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apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
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apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
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}
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static void disable_lapic_irq (unsigned int irq)
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@ -1643,7 +1643,7 @@ static void disable_lapic_irq (unsigned int irq)
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unsigned long v;
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v = apic_read(APIC_LVT0);
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apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
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apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
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}
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static void ack_lapic_irq (unsigned int irq)
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@ -1769,7 +1769,7 @@ static inline void check_timer(void)
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* the 8259A which implies the virtual wire has to be
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* disabled in the local APIC.
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*/
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apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
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apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
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init_8259A(1);
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enable_8259A_irq(0);
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@ -1835,21 +1835,21 @@ static inline void check_timer(void)
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disable_8259A_irq(0);
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irq_desc[0].handler = &lapic_irq_type;
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apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
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apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
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enable_8259A_irq(0);
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if (timer_irq_works()) {
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apic_printk(APIC_QUIET, " works.\n");
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return;
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}
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apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
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apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
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apic_printk(APIC_VERBOSE," failed.\n");
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apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
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init_8259A(0);
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make_8259A_irq(0);
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apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
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apic_write(APIC_LVT0, APIC_DM_EXTINT);
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unlock_ExtINT_logic();
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@ -80,7 +80,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
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h = THERMAL_APIC_VECTOR;
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h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
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apic_write_around(APIC_LVTTHMR, h);
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apic_write(APIC_LVTTHMR, h);
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rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
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wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
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@ -89,7 +89,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
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wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
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l = apic_read(APIC_LVTTHMR);
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apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
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cpu, tm2 ? "TM2" : "TM1");
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return;
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@ -666,7 +666,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta
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for (j = 1; j <= num_starts; j++) {
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Dprintk("Sending STARTUP #%d.\n",j);
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apic_read_around(APIC_SPIV);
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apic_write(APIC_ESR, 0);
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apic_read(APIC_ESR);
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Dprintk("After apic_write.\n");
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@ -705,7 +704,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta
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* Due to the Pentium erratum 3AP.
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*/
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if (maxlvt > 3) {
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apic_read_around(APIC_SPIV);
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apic_write(APIC_ESR, 0);
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}
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accept_status = (apic_read(APIC_ESR) & 0xEF);
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@ -842,11 +840,8 @@ do_rest:
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/*
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* Be paranoid about clearing APIC errors.
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*/
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if (APIC_INTEGRATED(apic_version[apicid])) {
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apic_read_around(APIC_SPIV);
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apic_write(APIC_ESR, 0);
|
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apic_read(APIC_ESR);
|
||||
}
|
||||
apic_write(APIC_ESR, 0);
|
||||
apic_read(APIC_ESR);
|
||||
|
||||
/*
|
||||
* Status is now clean
|
||||
|
|
@ -1024,7 +1019,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
|
|||
/*
|
||||
* If we couldn't find a local APIC, then get out of here now!
|
||||
*/
|
||||
if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
|
||||
if (!cpu_has_apic) {
|
||||
printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
|
||||
boot_cpu_id);
|
||||
printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
|
||||
|
|
|
|||
|
|
@ -52,10 +52,6 @@ static __inline__ void apic_wait_icr_idle(void)
|
|||
while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
|
||||
}
|
||||
|
||||
#define FORCE_READ_AROUND_WRITE 0
|
||||
#define apic_read_around(x)
|
||||
#define apic_write_around(x,y) apic_write((x),(y))
|
||||
|
||||
static inline void ack_APIC_irq(void)
|
||||
{
|
||||
/*
|
||||
|
|
@ -66,7 +62,7 @@ static inline void ack_APIC_irq(void)
|
|||
*/
|
||||
|
||||
/* Docs say use 0 for future compatibility */
|
||||
apic_write_around(APIC_EOI, 0);
|
||||
apic_write(APIC_EOI, 0);
|
||||
}
|
||||
|
||||
extern int get_maxlvt (void);
|
||||
|
|
|
|||
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