ixgbe: Defeature Tx Head writeback
Tx Head writeback is causing multi-microsecond stalls on PCIe chipsets, due to partial cacheline writebacks. Removing this feature removes these issues. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Родитель
0ecc061d19
Коммит
12207e498b
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@ -204,9 +204,6 @@ static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
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#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
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#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
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MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
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MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
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#define GET_TX_HEAD_FROM_RING(ring) (\
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*(volatile u32 *) \
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((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
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static void ixgbe_tx_timeout(struct net_device *netdev);
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static void ixgbe_tx_timeout(struct net_device *netdev);
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/**
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/**
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@ -217,26 +214,27 @@ static void ixgbe_tx_timeout(struct net_device *netdev);
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static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
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static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *tx_ring)
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struct ixgbe_ring *tx_ring)
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{
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{
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union ixgbe_adv_tx_desc *tx_desc;
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struct ixgbe_tx_buffer *tx_buffer_info;
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struct net_device *netdev = adapter->netdev;
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struct net_device *netdev = adapter->netdev;
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struct sk_buff *skb;
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union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
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unsigned int i;
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struct ixgbe_tx_buffer *tx_buffer_info;
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u32 head, oldhead;
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unsigned int i, eop, count = 0;
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unsigned int count = 0;
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unsigned int total_bytes = 0, total_packets = 0;
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unsigned int total_bytes = 0, total_packets = 0;
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rmb();
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head = GET_TX_HEAD_FROM_RING(tx_ring);
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head = le32_to_cpu(head);
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i = tx_ring->next_to_clean;
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i = tx_ring->next_to_clean;
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while (1) {
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eop = tx_ring->tx_buffer_info[i].next_to_watch;
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while (i != head) {
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eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
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while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
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(count < tx_ring->count)) {
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bool cleaned = false;
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for ( ; !cleaned; count++) {
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struct sk_buff *skb;
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tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
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tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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cleaned = (i == eop);
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skb = tx_buffer_info->skb;
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skb = tx_buffer_info->skb;
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if (skb) {
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if (cleaned && skb) {
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unsigned int segs, bytecount;
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unsigned int segs, bytecount;
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/* gso_segs is currently only valid for tcp */
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/* gso_segs is currently only valid for tcp */
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@ -251,23 +249,17 @@ static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
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ixgbe_unmap_and_free_tx_resource(adapter,
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ixgbe_unmap_and_free_tx_resource(adapter,
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tx_buffer_info);
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tx_buffer_info);
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tx_desc->wb.status = 0;
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i++;
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i++;
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if (i == tx_ring->count)
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if (i == tx_ring->count)
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i = 0;
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i = 0;
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count++;
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if (count == tx_ring->count)
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goto done_cleaning;
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}
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}
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oldhead = head;
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rmb();
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head = GET_TX_HEAD_FROM_RING(tx_ring);
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head = le32_to_cpu(head);
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if (head == oldhead)
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goto done_cleaning;
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} /* while (1) */
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done_cleaning:
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eop = tx_ring->tx_buffer_info[i].next_to_watch;
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eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
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}
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tx_ring->next_to_clean = i;
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tx_ring->next_to_clean = i;
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#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
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#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
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@ -301,8 +293,8 @@ done_cleaning:
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tx_ring->total_bytes += total_bytes;
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tx_ring->total_bytes += total_bytes;
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tx_ring->total_packets += total_packets;
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tx_ring->total_packets += total_packets;
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tx_ring->stats.bytes += total_bytes;
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tx_ring->stats.packets += total_packets;
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tx_ring->stats.packets += total_packets;
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tx_ring->stats.bytes += total_bytes;
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adapter->net_stats.tx_bytes += total_bytes;
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adapter->net_stats.tx_bytes += total_bytes;
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adapter->net_stats.tx_packets += total_packets;
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adapter->net_stats.tx_packets += total_packets;
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return (total_packets ? true : false);
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return (total_packets ? true : false);
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@ -1484,7 +1476,7 @@ static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
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**/
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**/
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static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
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static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
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{
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{
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u64 tdba, tdwba;
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u64 tdba;
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struct ixgbe_hw *hw = &adapter->hw;
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struct ixgbe_hw *hw = &adapter->hw;
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u32 i, j, tdlen, txctrl;
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u32 i, j, tdlen, txctrl;
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@ -1497,11 +1489,6 @@ static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
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IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
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IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
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(tdba & DMA_32BIT_MASK));
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(tdba & DMA_32BIT_MASK));
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IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
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IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
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tdwba = ring->dma +
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(ring->count * sizeof(union ixgbe_adv_tx_desc));
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tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
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IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
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IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
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IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
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IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
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IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
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IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
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IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
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IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
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@ -2880,8 +2867,7 @@ int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
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memset(tx_ring->tx_buffer_info, 0, size);
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memset(tx_ring->tx_buffer_info, 0, size);
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/* round up to nearest 4K */
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/* round up to nearest 4K */
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tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
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tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
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sizeof(u32);
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tx_ring->size = ALIGN(tx_ring->size, 4096);
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tx_ring->size = ALIGN(tx_ring->size, 4096);
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tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
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tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
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