ASoC: qcom: Add common array to initialize soc based core clocks
LPASS variants have their own soc specific clocks that needs to be enabled for MI2S audio support. Added a common variable in drvdata to initialize such clocks using bulk clk api. Such clock names is defined in variants specific data and needs to fetched during init. Signed-off-by: Ajit Pandey <ajitp@codeaurora.org> Signed-off-by: Rohit kumar <rohitkr@codeaurora.org> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/1597402388-14112-2-git-send-email-rohitkr@codeaurora.org Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -161,32 +161,27 @@ static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan)
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static int apq8016_lpass_init(struct platform_device *pdev)
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{
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struct lpass_data *drvdata = platform_get_drvdata(pdev);
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struct lpass_variant *variant = drvdata->variant;
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struct device *dev = &pdev->dev;
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int ret;
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int ret, i;
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drvdata->pcnoc_mport_clk = devm_clk_get(dev, "pcnoc-mport-clk");
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if (IS_ERR(drvdata->pcnoc_mport_clk)) {
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dev_err(dev, "error getting pcnoc-mport-clk: %ld\n",
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PTR_ERR(drvdata->pcnoc_mport_clk));
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return PTR_ERR(drvdata->pcnoc_mport_clk);
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}
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ret = clk_prepare_enable(drvdata->pcnoc_mport_clk);
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drvdata->clks = devm_kcalloc(dev, variant->num_clks,
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sizeof(*drvdata->clks), GFP_KERNEL);
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drvdata->num_clks = variant->num_clks;
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for (i = 0; i < drvdata->num_clks; i++)
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drvdata->clks[i].id = variant->clk_name[i];
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ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
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if (ret) {
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dev_err(dev, "Error enabling pcnoc-mport-clk: %d\n", ret);
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dev_err(dev, "Failed to get clocks %d\n", ret);
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return ret;
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}
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drvdata->pcnoc_sway_clk = devm_clk_get(dev, "pcnoc-sway-clk");
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if (IS_ERR(drvdata->pcnoc_sway_clk)) {
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dev_err(dev, "error getting pcnoc-sway-clk: %ld\n",
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PTR_ERR(drvdata->pcnoc_sway_clk));
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return PTR_ERR(drvdata->pcnoc_sway_clk);
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}
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ret = clk_prepare_enable(drvdata->pcnoc_sway_clk);
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ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
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if (ret) {
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dev_err(dev, "Error enabling pcnoc_sway_clk: %d\n", ret);
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dev_err(dev, "apq8016 clk_enable failed\n");
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return ret;
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}
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@ -197,8 +192,7 @@ static int apq8016_lpass_exit(struct platform_device *pdev)
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{
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struct lpass_data *drvdata = platform_get_drvdata(pdev);
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clk_disable_unprepare(drvdata->pcnoc_mport_clk);
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clk_disable_unprepare(drvdata->pcnoc_sway_clk);
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clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
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return 0;
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}
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@ -219,6 +213,11 @@ static struct lpass_variant apq8016_data = {
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.wrdma_reg_stride = 0x1000,
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.wrdma_channel_start = 5,
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.wrdma_channels = 2,
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.clk_name = (const char*[]) {
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"pcnoc-mport-clk",
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"pcnoc-sway-clk",
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},
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.num_clks = 2,
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.dai_driver = apq8016_lpass_cpu_dai_driver,
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.num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver),
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.dai_osr_clk_names = (const char *[]) {
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@ -51,9 +51,9 @@ struct lpass_data {
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/* used it for handling interrupt per dma channel */
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struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
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/* 8016 specific */
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struct clk *pcnoc_mport_clk;
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struct clk *pcnoc_sway_clk;
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/* SOC specific clock list */
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struct clk_bulk_data *clks;
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int num_clks;
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};
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@ -89,6 +89,10 @@ struct lpass_variant {
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int num_dai;
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const char * const *dai_osr_clk_names;
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const char * const *dai_bit_clk_names;
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/* SOC specific clocks configuration */
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const char **clk_name;
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int num_clks;
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};
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/* register the platform driver from the CPU DAI driver */
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