drm/radeon: s/ioctl_wait_idle/mmio_hpd_flush/
And clean up the function comment a little. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer
Alex Deucher
Родитель
f28be81011
Коммит
124764f174
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@ -4088,16 +4088,15 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
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}
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/**
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* r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
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* r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
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* rdev: radeon device structure
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* bo: buffer object struct which userspace is waiting for idle
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*
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* Some R6XX/R7XX doesn't seems to take into account HDP flush performed
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* through ring buffer, this leads to corruption in rendering, see
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* http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
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* directly perform HDP flush by writing register through MMIO.
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* Some R6XX/R7XX don't seem to take into account HDP flushes performed
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* through the ring buffer. This leads to corruption in rendering, see
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* http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
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* directly perform the HDP flush by writing the register through MMIO.
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*/
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void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
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void r600_mmio_hdp_flush(struct radeon_device *rdev)
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{
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/* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
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* rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
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@ -1772,13 +1772,8 @@ struct radeon_asic {
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int (*suspend)(struct radeon_device *rdev);
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void (*vga_set_state)(struct radeon_device *rdev, bool state);
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int (*asic_reset)(struct radeon_device *rdev);
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/* ioctl hw specific callback. Some hw might want to perform special
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* operation on specific ioctl. For instance on wait idle some hw
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* might want to perform and HDP flush through MMIO as it seems that
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* some R6XX/R7XX hw doesn't take HDP flush into account if programmed
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* through ring.
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*/
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void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
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/* Flush the HDP cache via MMIO */
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void (*mmio_hdp_flush)(struct radeon_device *rdev);
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/* check if 3D engine is idle */
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bool (*gui_idle)(struct radeon_device *rdev);
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/* wait for mc_idle */
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@ -194,7 +194,7 @@ static struct radeon_asic r100_asic = {
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.resume = &r100_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &r100_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r100_mc_wait_for_idle,
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.gart = {
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@ -260,7 +260,7 @@ static struct radeon_asic r200_asic = {
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.resume = &r100_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &r100_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r100_mc_wait_for_idle,
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.gart = {
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@ -340,7 +340,7 @@ static struct radeon_asic r300_asic = {
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.resume = &r300_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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.gart = {
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@ -406,7 +406,7 @@ static struct radeon_asic r300_asic_pcie = {
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.resume = &r300_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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.gart = {
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@ -472,7 +472,7 @@ static struct radeon_asic r420_asic = {
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.resume = &r420_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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.gart = {
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@ -538,7 +538,7 @@ static struct radeon_asic rs400_asic = {
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.resume = &rs400_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rs400_mc_wait_for_idle,
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.gart = {
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@ -604,7 +604,7 @@ static struct radeon_asic rs600_asic = {
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.resume = &rs600_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rs600_mc_wait_for_idle,
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.gart = {
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@ -672,7 +672,7 @@ static struct radeon_asic rs690_asic = {
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.resume = &rs690_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rs690_mc_wait_for_idle,
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.gart = {
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@ -740,7 +740,7 @@ static struct radeon_asic rv515_asic = {
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.resume = &rv515_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rv515_mc_wait_for_idle,
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.gart = {
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@ -806,7 +806,7 @@ static struct radeon_asic r520_asic = {
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.resume = &r520_resume,
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.vga_set_state = &r100_vga_set_state,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r520_mc_wait_for_idle,
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.gart = {
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@ -898,7 +898,7 @@ static struct radeon_asic r600_asic = {
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.resume = &r600_resume,
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.vga_set_state = &r600_vga_set_state,
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.asic_reset = &r600_asic_reset,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &r600_mc_wait_for_idle,
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.get_xclk = &r600_get_xclk,
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@ -970,7 +970,7 @@ static struct radeon_asic rv6xx_asic = {
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.resume = &r600_resume,
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.vga_set_state = &r600_vga_set_state,
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.asic_reset = &r600_asic_reset,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &r600_mc_wait_for_idle,
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.get_xclk = &r600_get_xclk,
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@ -1060,7 +1060,7 @@ static struct radeon_asic rs780_asic = {
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.resume = &r600_resume,
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.vga_set_state = &r600_vga_set_state,
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.asic_reset = &r600_asic_reset,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &r600_mc_wait_for_idle,
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.get_xclk = &r600_get_xclk,
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@ -1163,7 +1163,7 @@ static struct radeon_asic rv770_asic = {
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.resume = &rv770_resume,
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.asic_reset = &r600_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &r600_mc_wait_for_idle,
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.get_xclk = &rv770_get_xclk,
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@ -1281,7 +1281,7 @@ static struct radeon_asic evergreen_asic = {
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.resume = &evergreen_resume,
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.asic_reset = &evergreen_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &rv770_get_xclk,
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@ -1373,7 +1373,7 @@ static struct radeon_asic sumo_asic = {
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.resume = &evergreen_resume,
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.asic_reset = &evergreen_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &r600_get_xclk,
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@ -1464,7 +1464,7 @@ static struct radeon_asic btc_asic = {
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.resume = &evergreen_resume,
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.asic_reset = &evergreen_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &rv770_get_xclk,
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@ -1599,7 +1599,7 @@ static struct radeon_asic cayman_asic = {
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.resume = &cayman_resume,
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.asic_reset = &cayman_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &rv770_get_xclk,
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@ -1699,7 +1699,7 @@ static struct radeon_asic trinity_asic = {
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.resume = &cayman_resume,
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.asic_reset = &cayman_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &r600_get_xclk,
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@ -1829,7 +1829,7 @@ static struct radeon_asic si_asic = {
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.resume = &si_resume,
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.asic_reset = &si_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.mmio_hdp_flush = r600_mmio_hdp_flush,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &si_get_xclk,
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@ -1987,7 +1987,7 @@ static struct radeon_asic ci_asic = {
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.resume = &cik_resume,
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.asic_reset = &cik_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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@ -2091,7 +2091,7 @@ static struct radeon_asic kv_asic = {
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.resume = &cik_resume,
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.asic_reset = &cik_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.ioctl_wait_idle = NULL,
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.mmio_hdp_flush = NULL,
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.gui_idle = &r600_gui_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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@ -351,7 +351,7 @@ void r600_hpd_fini(struct radeon_device *rdev);
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bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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void r600_hpd_set_polarity(struct radeon_device *rdev,
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enum radeon_hpd_id hpd);
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extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
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extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
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extern bool r600_gui_idle(struct radeon_device *rdev);
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extern void r600_pm_misc(struct radeon_device *rdev);
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extern void r600_pm_init_profile(struct radeon_device *rdev);
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@ -365,9 +365,9 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
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}
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robj = gem_to_radeon_bo(gobj);
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r = radeon_bo_wait(robj, NULL, false);
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/* callback hw specific functions if any */
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if (rdev->asic->ioctl_wait_idle)
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robj->rdev->asic->ioctl_wait_idle(rdev, robj);
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/* Flush HDP cache via MMIO if necessary */
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if (rdev->asic->mmio_hdp_flush)
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robj->rdev->asic->mmio_hdp_flush(rdev);
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drm_gem_object_unreference_unlocked(gobj);
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r = radeon_gem_handle_lockup(rdev, r);
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return r;
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