iwlwifi: hw names cleanup
This patch make some cleanup in HW names Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Tomas Winkler
John W. Linville
Родитель
133adf0826
Коммит
12a81f60b9
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@ -126,16 +126,18 @@
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/* Sizes and addresses for instruction and data memory (SRAM) in
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* 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
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#define RTC_INST_LOWER_BOUND (0x000000)
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#define KDR_RTC_INST_UPPER_BOUND (0x018000)
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#define IWL49_RTC_INST_UPPER_BOUND (0x018000)
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#define RTC_DATA_LOWER_BOUND (0x800000)
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#define KDR_RTC_DATA_UPPER_BOUND (0x80A000)
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#define IWL49_RTC_DATA_UPPER_BOUND (0x80A000)
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#define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
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#define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
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#define IWL49_RTC_INST_SIZE \
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(IWL49_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
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#define IWL49_RTC_DATA_SIZE \
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(IWL49_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
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#define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE
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#define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE
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#define IWL_MAX_INST_SIZE IWL49_RTC_INST_SIZE
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#define IWL_MAX_DATA_SIZE IWL49_RTC_DATA_SIZE
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/* Size of uCode instruction memory in bootstrap state machine */
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#define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
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@ -143,7 +145,7 @@
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static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr)
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{
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return (addr >= RTC_DATA_LOWER_BOUND) &&
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(addr < KDR_RTC_DATA_UPPER_BOUND);
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(addr < IWL49_RTC_DATA_UPPER_BOUND);
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}
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/********************* START TEMPERATURE *************************************/
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@ -532,7 +532,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
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}
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/* Turn off all Tx DMA channels */
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iwl_write_prph(priv, KDR_SCD_TXFACT, 0);
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iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -1731,7 +1731,7 @@ static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
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{
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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(index & 0xff) | (txq_id << 8));
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iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
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iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
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}
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/**
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@ -1751,7 +1751,7 @@ static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
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int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
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/* Set up and activate */
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iwl_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
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iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
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(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
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(scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
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@ -1810,7 +1810,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
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}
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/* Clear 4965's internal Tx Scheduler data base */
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priv->scd_base_addr = iwl_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
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priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
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a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
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for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
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iwl_write_targ_mem(priv, a, 0);
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@ -1820,18 +1820,18 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
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iwl_write_targ_mem(priv, a, 0);
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/* Tel 4965 where to find Tx byte count tables */
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iwl_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
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iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
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(priv->hw_setting.shared_phys +
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offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
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/* Disable chain mode for all queues */
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iwl_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
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iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
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/* Initialize each Tx queue (including the command queue) */
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for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
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/* TFD circular buffer read/write indexes */
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iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
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iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
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iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
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/* Max Tx Window size for Scheduler-ACK mode */
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@ -1850,11 +1850,11 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
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}
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iwl_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
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iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
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(1 << priv->hw_setting.max_txq_num) - 1);
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/* Activate all Tx DMA/FIFO channels */
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iwl_write_prph(priv, KDR_SCD_TXFACT,
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iwl_write_prph(priv, IWL49_SCD_TXFACT,
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SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
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iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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@ -4091,7 +4091,7 @@ static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
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/* Simply stop the queue, but don't change any configuration;
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* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
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iwl_write_prph(priv,
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KDR_SCD_QUEUE_STATUS_BITS(txq_id),
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IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
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(0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
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(1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
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}
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@ -4117,14 +4117,14 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
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iwl4965_tx_queue_stop_scheduler(priv, txq_id);
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iwl_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
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iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
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priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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/* supposes that ssn_idx is valid (!= 0xFFF) */
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iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
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iwl_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl4965_txq_ctx_deactivate(priv, txq_id);
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iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
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@ -4313,7 +4313,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
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iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
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/* Set this queue as a chain-building queue */
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iwl_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
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iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
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/* Place first TFD at index corresponding to start sequence number.
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* Assumes that ssn_idx is valid (!= 0xFFF) */
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@ -4332,7 +4332,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
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(SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
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& SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
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iwl_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
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/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
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@ -243,44 +243,48 @@
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* 4965 Tx Scheduler registers.
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* Details are documented in iwl-4965-hw.h
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*/
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#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define IWL49_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0)
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#define KDR_SCD_EMPTY_BITS (KDR_SCD_BASE + 0x4)
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#define KDR_SCD_DRAM_BASE_ADDR (KDR_SCD_BASE + 0x10)
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#define KDR_SCD_AIT (KDR_SCD_BASE + 0x18)
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#define KDR_SCD_TXFACT (KDR_SCD_BASE + 0x1c)
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#define KDR_SCD_QUEUE_WRPTR(x) (KDR_SCD_BASE + 0x24 + (x) * 4)
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#define KDR_SCD_QUEUE_RDPTR(x) (KDR_SCD_BASE + 0x64 + (x) * 4)
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#define KDR_SCD_SETQUEUENUM (KDR_SCD_BASE + 0xa4)
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#define KDR_SCD_SET_TXSTAT_TXED (KDR_SCD_BASE + 0xa8)
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#define KDR_SCD_SET_TXSTAT_DONE (KDR_SCD_BASE + 0xac)
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#define KDR_SCD_SET_TXSTAT_NOT_SCHD (KDR_SCD_BASE + 0xb0)
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#define KDR_SCD_DECREASE_CREDIT (KDR_SCD_BASE + 0xb4)
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#define KDR_SCD_DECREASE_SCREDIT (KDR_SCD_BASE + 0xb8)
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#define KDR_SCD_LOAD_CREDIT (KDR_SCD_BASE + 0xbc)
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#define KDR_SCD_LOAD_SCREDIT (KDR_SCD_BASE + 0xc0)
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#define KDR_SCD_BAR (KDR_SCD_BASE + 0xc4)
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#define KDR_SCD_BAR_DW0 (KDR_SCD_BASE + 0xc8)
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#define KDR_SCD_BAR_DW1 (KDR_SCD_BASE + 0xcc)
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#define KDR_SCD_QUEUECHAIN_SEL (KDR_SCD_BASE + 0xd0)
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#define KDR_SCD_QUERY_REQ (KDR_SCD_BASE + 0xd8)
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#define KDR_SCD_QUERY_RES (KDR_SCD_BASE + 0xdc)
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#define KDR_SCD_PENDING_FRAMES (KDR_SCD_BASE + 0xe0)
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#define KDR_SCD_INTERRUPT_MASK (KDR_SCD_BASE + 0xe4)
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#define KDR_SCD_INTERRUPT_THRESHOLD (KDR_SCD_BASE + 0xe8)
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#define KDR_SCD_QUERY_MIN_FRAME_SIZE (KDR_SCD_BASE + 0x100)
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#define KDR_SCD_QUEUE_STATUS_BITS(x) (KDR_SCD_BASE + 0x104 + (x) * 4)
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#define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_BASE + 0x0)
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#define IWL49_SCD_EMPTY_BITS (IWL49_SCD_BASE + 0x4)
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#define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_BASE + 0x10)
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#define IWL49_SCD_AIT (IWL49_SCD_BASE + 0x18)
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#define IWL49_SCD_TXFACT (IWL49_SCD_BASE + 0x1c)
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#define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_BASE + 0x24 + (x) * 4)
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#define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_BASE + 0x64 + (x) * 4)
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#define IWL49_SCD_SETQUEUENUM (IWL49_SCD_BASE + 0xa4)
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#define IWL49_SCD_SET_TXSTAT_TXED (IWL49_SCD_BASE + 0xa8)
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#define IWL49_SCD_SET_TXSTAT_DONE (IWL49_SCD_BASE + 0xac)
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#define IWL49_SCD_SET_TXSTAT_NOT_SCHD (IWL49_SCD_BASE + 0xb0)
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#define IWL49_SCD_DECREASE_CREDIT (IWL49_SCD_BASE + 0xb4)
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#define IWL49_SCD_DECREASE_SCREDIT (IWL49_SCD_BASE + 0xb8)
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#define IWL49_SCD_LOAD_CREDIT (IWL49_SCD_BASE + 0xbc)
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#define IWL49_SCD_LOAD_SCREDIT (IWL49_SCD_BASE + 0xc0)
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#define IWL49_SCD_BAR (IWL49_SCD_BASE + 0xc4)
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#define IWL49_SCD_BAR_DW0 (IWL49_SCD_BASE + 0xc8)
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#define IWL49_SCD_BAR_DW1 (IWL49_SCD_BASE + 0xcc)
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#define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_BASE + 0xd0)
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#define IWL49_SCD_QUERY_REQ (IWL49_SCD_BASE + 0xd8)
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#define IWL49_SCD_QUERY_RES (IWL49_SCD_BASE + 0xdc)
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#define IWL49_SCD_PENDING_FRAMES (IWL49_SCD_BASE + 0xe0)
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#define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_BASE + 0xe4)
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#define IWL49_SCD_INTERRUPT_THRESHOLD (IWL49_SCD_BASE + 0xe8)
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#define IWL49_SCD_QUERY_MIN_FRAME_SIZE (IWL49_SCD_BASE + 0x100)
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#define IWL49_SCD_QUEUE_STATUS_BITS(x) (IWL49_SCD_BASE + 0x104 + (x) * 4)
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/* SP SCD */
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#define SHL_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define SHL_SCD_AIT (SHL_SCD_BASE + 0x0c)
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#define SHL_SCD_TXFACT (SHL_SCD_BASE + 0x10)
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#define SHL_SCD_QUEUE_WRPTR(x) (SHL_SCD_BASE + 0x18 + (x) * 4)
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#define SHL_SCD_QUEUE_RDPTR(x) (SHL_SCD_BASE + 0x68 + (x) * 4)
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#define SHL_SCD_QUEUECHAIN_SEL (SHL_SCD_BASE + 0xe8)
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#define SHL_SCD_AGGR_SEL (SHL_SCD_BASE + 0x248)
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#define SHL_SCD_INTERRUPT_MASK (SHL_SCD_BASE + 0x108)
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#define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0)
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#define IWL50_SCD_DRAM_BASE_ADDR (IWL50_SCD_BASE + 0x8)
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#define IWL50_SCD_AIT (IWL50_SCD_BASE + 0x0c)
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#define IWL50_SCD_TXFACT (IWL50_SCD_BASE + 0x10)
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#define IWL50_SCD_ACTIVE (IWL50_SCD_BASE + 0x14)
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#define IWL50_SCD_QUEUE_WRPTR(x) (IWL50_SCD_BASE + 0x18 + (x) * 4)
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#define IWL50_SCD_QUEUE_RDPTR(x) (IWL50_SCD_BASE + 0x68 + (x) * 4)
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#define IWL50_SCD_QUEUECHAIN_SEL (IWL50_SCD_BASE + 0xe8)
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#define IWL50_SCD_AGGR_SEL (IWL50_SCD_BASE + 0x248)
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#define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108)
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#define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4)
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#endif /* __iwl_prph_h__ */
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