MIPS: Add driver for the built-in PCI controller of the RT3883 SoC
The Ralink RT3883 SoCs have a built-in PCI Host Controller device. The patch adds a platform driver and device tree binding documentation for that. The patch also enables the HW_HAS_PCI config option. This is required in order to be able to enable the PCI support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Gabor Juhos
Ralf Baechle
Родитель
f86f55d3ad
Коммит
12d14e0edd
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@ -0,0 +1,190 @@
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* Mediatek/Ralink RT3883 PCI controller
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1) Main node
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Required properties:
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- compatible: must be "ralink,rt3883-pci"
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- reg: specifies the physical base address of the controller and
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the length of the memory mapped region.
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 1.
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- #size-cells: specifies the number of cells used to represent the size
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of an address. The value must be 1.
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- ranges: specifies the translation between child address space and parent
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address space
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Optional properties:
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- status: indicates the operational status of the device.
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Value must be either "disabled" or "okay".
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2) Child nodes
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The main node must have two child nodes which describes the built-in
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interrupt controller and the PCI host bridge.
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a) Interrupt controller:
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Required properties:
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- interrupt-controller: identifies the node as an interrupt controller
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0. As such, 'interrupt-map' nodes do not
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have to specify a parent unit address.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- interrupt-parent: the phandle for the interrupt controller that
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services interrupts for this device.
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends on the
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parent interrupt controller.
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b) PCI host bridge:
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Required properties:
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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- #size-cells: specifies the number of cells used to represent the size
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of an address. The value must be 2.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- device_type: must be "pci"
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- bus-range: PCI bus numbers covered
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- ranges: specifies the ranges for the PCI memory and I/O regions
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- interrupt-map-mask,
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- interrupt-map: standard PCI properties to define the mapping of the
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PCI interface to interrupt numbers.
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The PCI host bridge node migh have additional sub-nodes representing
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the onboard PCI devices/PCI slots. Each such sub-node must have the
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following mandatory properties:
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- reg: used only for interrupt mapping, so only the first four bytes
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are used to refer to the correct bus number and device number.
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- device_type: must be "pci"
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If a given sub-node represents a PCI bridge it must have following
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mandatory properties as well:
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- #address-cells: must be set to <3>
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- #size-cells: must set to <2>
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- #interrupt-cells: must be set to <1>
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- interrupt-map-mask,
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- interrupt-map: standard PCI properties to define the mapping of the
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PCI interface to interrupt numbers.
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Besides the required properties the sub-nodes may have these optional
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properties:
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- status: indicates the operational status of the sub-node.
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Value must be either "disabled" or "okay".
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3) Example:
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a) SoC specific dtsi file:
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pci@10140000 {
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compatible = "ralink,rt3883-pci";
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reg = <0x10140000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges; /* direct mapping */
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status = "disabled";
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pciintc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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};
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host-bridge {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
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>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 17 */
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0x8800 0 0 1 &pciintc 18
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0x8800 0 0 2 &pciintc 18
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0x8800 0 0 3 &pciintc 18
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0x8800 0 0 4 &pciintc 18
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/* IDSEL 18 */
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0x9000 0 0 1 &pciintc 19
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0x9000 0 0 2 &pciintc 19
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0x9000 0 0 3 &pciintc 19
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0x9000 0 0 4 &pciintc 19
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>;
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pci-bridge@1 {
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reg = <0x0800 0 0 0 0>;
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device_type = "pci";
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#interrupt-cells = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0x0 0 0 0>;
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interrupt-map = <0x0 0 0 0 &pciintc 20>;
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status = "disabled";
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};
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pci-slot@17 {
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reg = <0x8800 0 0 0 0>;
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device_type = "pci";
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status = "disabled";
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};
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pci-slot@18 {
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reg = <0x9000 0 0 0 0>;
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device_type = "pci";
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status = "disabled";
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};
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};
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};
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b) Board specific dts file:
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pci@10140000 {
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status = "okay";
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host-bridge {
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pci-bridge@1 {
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status = "okay";
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};
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};
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};
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@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
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obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
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obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
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obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
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obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
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obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
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obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
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obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
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@ -0,0 +1,636 @@
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/*
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* Ralink RT3662/RT3883 SoC PCI support
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*
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* Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ralink/rt3883.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#define RT3883_MEMORY_BASE 0x00000000
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#define RT3883_MEMORY_SIZE 0x02000000
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#define RT3883_PCI_REG_PCICFG 0x00
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#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
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#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
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#define RT3883_PCICFG_PCIRST BIT(1)
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#define RT3883_PCI_REG_PCIRAW 0x04
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#define RT3883_PCI_REG_PCIINT 0x08
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#define RT3883_PCI_REG_PCIENA 0x0c
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#define RT3883_PCI_REG_CFGADDR 0x20
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#define RT3883_PCI_REG_CFGDATA 0x24
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#define RT3883_PCI_REG_MEMBASE 0x28
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#define RT3883_PCI_REG_IOBASE 0x2c
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#define RT3883_PCI_REG_ARBCTL 0x80
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#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
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#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
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#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
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#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
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#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
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#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
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#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
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#define RT3883_PCI_MODE_NONE 0
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#define RT3883_PCI_MODE_PCI BIT(0)
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#define RT3883_PCI_MODE_PCIE BIT(1)
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#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
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#define RT3883_PCI_IRQ_COUNT 32
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#define RT3883_P2P_BR_DEVNUM 1
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struct rt3883_pci_controller {
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void __iomem *base;
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spinlock_t lock;
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struct device_node *intc_of_node;
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struct irq_domain *irq_domain;
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struct pci_controller pci_controller;
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struct resource io_res;
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struct resource mem_res;
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bool pcie_ready;
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};
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static inline struct rt3883_pci_controller *
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pci_bus_to_rt3883_controller(struct pci_bus *bus)
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{
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struct pci_controller *hose;
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hose = (struct pci_controller *) bus->sysdata;
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return container_of(hose, struct rt3883_pci_controller, pci_controller);
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}
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static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
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unsigned reg)
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{
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return ioread32(rpc->base + reg);
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}
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static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
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u32 val, unsigned reg)
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{
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iowrite32(val, rpc->base + reg);
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}
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static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
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unsigned int func, unsigned int where)
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{
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return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
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0x80000000;
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}
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static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
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unsigned bus, unsigned slot,
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unsigned func, unsigned reg)
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{
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unsigned long flags;
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u32 address;
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u32 ret;
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address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
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spin_lock_irqsave(&rpc->lock, flags);
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rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
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ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
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spin_unlock_irqrestore(&rpc->lock, flags);
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return ret;
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}
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static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
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unsigned bus, unsigned slot,
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unsigned func, unsigned reg, u32 val)
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{
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unsigned long flags;
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u32 address;
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address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
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spin_lock_irqsave(&rpc->lock, flags);
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rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
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rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
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spin_unlock_irqrestore(&rpc->lock, flags);
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}
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static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct rt3883_pci_controller *rpc;
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u32 pending;
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rpc = irq_get_handler_data(irq);
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pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
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rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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if (!pending) {
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spurious_interrupt();
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return;
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}
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while (pending) {
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unsigned bit = __ffs(pending);
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irq = irq_find_mapping(rpc->irq_domain, bit);
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generic_handle_irq(irq);
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pending &= ~BIT(bit);
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}
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}
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static void rt3883_pci_irq_unmask(struct irq_data *d)
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{
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struct rt3883_pci_controller *rpc;
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u32 t;
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rpc = irq_data_get_irq_chip_data(d);
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t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
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/* flush write */
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rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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}
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static void rt3883_pci_irq_mask(struct irq_data *d)
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{
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struct rt3883_pci_controller *rpc;
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u32 t;
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rpc = irq_data_get_irq_chip_data(d);
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t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
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/* flush write */
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rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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}
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static struct irq_chip rt3883_pci_irq_chip = {
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.name = "RT3883 PCI",
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.irq_mask = rt3883_pci_irq_mask,
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.irq_unmask = rt3883_pci_irq_unmask,
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.irq_mask_ack = rt3883_pci_irq_mask,
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};
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static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
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.map = rt3883_pci_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int rt3883_pci_irq_init(struct device *dev,
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struct rt3883_pci_controller *rpc)
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{
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int irq;
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irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
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if (irq == 0) {
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dev_err(dev, "%s has no IRQ",
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of_node_full_name(rpc->intc_of_node));
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return -EINVAL;
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}
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/* disable all interrupts */
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rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
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rpc->irq_domain =
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irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
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&rt3883_pci_irq_domain_ops,
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rpc);
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if (!rpc->irq_domain) {
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dev_err(dev, "unable to add IRQ domain\n");
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return -ENODEV;
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}
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irq_set_handler_data(irq, rpc);
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irq_set_chained_handler(irq, rt3883_pci_irq_handler);
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return 0;
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}
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static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct rt3883_pci_controller *rpc;
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unsigned long flags;
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u32 address;
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u32 data;
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rpc = pci_bus_to_rt3883_controller(bus);
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if (!rpc->pcie_ready && bus->number == 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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spin_lock_irqsave(&rpc->lock, flags);
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rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
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data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
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spin_unlock_irqrestore(&rpc->lock, flags);
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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||||
*val = (data >> ((where & 3) << 3)) & 0xffff;
|
||||
break;
|
||||
case 4:
|
||||
*val = data;
|
||||
break;
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
struct rt3883_pci_controller *rpc;
|
||||
unsigned long flags;
|
||||
u32 address;
|
||||
u32 data;
|
||||
|
||||
rpc = pci_bus_to_rt3883_controller(bus);
|
||||
|
||||
if (!rpc->pcie_ready && bus->number == 1)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
PCI_FUNC(devfn), where);
|
||||
|
||||
spin_lock_irqsave(&rpc->lock, flags);
|
||||
rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
data = (data & ~(0xff << ((where & 3) << 3))) |
|
||||
(val << ((where & 3) << 3));
|
||||
break;
|
||||
case 2:
|
||||
data = (data & ~(0xffff << ((where & 3) << 3))) |
|
||||
(val << ((where & 3) << 3));
|
||||
break;
|
||||
case 4:
|
||||
data = val;
|
||||
break;
|
||||
}
|
||||
|
||||
rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
|
||||
spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static struct pci_ops rt3883_pci_ops = {
|
||||
.read = rt3883_pci_config_read,
|
||||
.write = rt3883_pci_config_write,
|
||||
};
|
||||
|
||||
static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
|
||||
{
|
||||
u32 syscfg1;
|
||||
u32 rstctrl;
|
||||
u32 clkcfg1;
|
||||
u32 t;
|
||||
|
||||
rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
|
||||
syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
|
||||
clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
|
||||
|
||||
if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
rstctrl |= RT3883_RSTCTRL_PCIE;
|
||||
rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
|
||||
/* setup PCI PAD drive mode */
|
||||
syscfg1 &= ~(0x30);
|
||||
syscfg1 |= (2 << 4);
|
||||
rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
|
||||
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
t &= ~BIT(31);
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
t &= 0x80ffffff;
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
t |= 0xa << 24;
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
t |= BIT(31);
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
|
||||
msleep(50);
|
||||
|
||||
rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
}
|
||||
|
||||
syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
|
||||
|
||||
clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
|
||||
|
||||
if (mode & RT3883_PCI_MODE_PCI) {
|
||||
clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
|
||||
rstctrl &= ~RT3883_RSTCTRL_PCI;
|
||||
}
|
||||
|
||||
if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
|
||||
rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
}
|
||||
|
||||
rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
|
||||
rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
|
||||
|
||||
msleep(500);
|
||||
|
||||
/*
|
||||
* setup the device number of the P2P bridge
|
||||
* and de-assert the reset line
|
||||
*/
|
||||
t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
|
||||
rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
|
||||
|
||||
/* flush write */
|
||||
rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
|
||||
msleep(500);
|
||||
|
||||
if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
msleep(500);
|
||||
|
||||
t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
|
||||
|
||||
rpc->pcie_ready = t & BIT(0);
|
||||
|
||||
if (!rpc->pcie_ready) {
|
||||
/* reset the PCIe block */
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
|
||||
t |= RT3883_RSTCTRL_PCIE;
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
|
||||
t &= ~RT3883_RSTCTRL_PCIE;
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
|
||||
|
||||
/* turn off PCIe clock */
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
|
||||
t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
|
||||
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
t &= ~0xf000c080;
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
}
|
||||
}
|
||||
|
||||
/* enable PCI arbiter */
|
||||
rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
|
||||
}
|
||||
|
||||
static int rt3883_pci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rt3883_pci_controller *rpc;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource *res;
|
||||
struct device_node *child;
|
||||
u32 val;
|
||||
int err;
|
||||
int mode;
|
||||
|
||||
rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
|
||||
if (!rpc)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
|
||||
rpc->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(rpc->base))
|
||||
return PTR_ERR(rpc->base);
|
||||
|
||||
/* find the interrupt controller child node */
|
||||
for_each_child_of_node(np, child) {
|
||||
if (of_get_property(child, "interrupt-controller", NULL) &&
|
||||
of_node_get(child)) {
|
||||
rpc->intc_of_node = child;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!rpc->intc_of_node) {
|
||||
dev_err(dev, "%s has no %s child node",
|
||||
of_node_full_name(rpc->intc_of_node),
|
||||
"interrupt controller");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* find the PCI host bridge child node */
|
||||
for_each_child_of_node(np, child) {
|
||||
if (child->type &&
|
||||
of_node_cmp(child->type, "pci") == 0 &&
|
||||
of_node_get(child)) {
|
||||
rpc->pci_controller.of_node = child;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!rpc->pci_controller.of_node) {
|
||||
dev_err(dev, "%s has no %s child node",
|
||||
of_node_full_name(rpc->intc_of_node),
|
||||
"PCI host bridge");
|
||||
err = -EINVAL;
|
||||
goto err_put_intc_node;
|
||||
}
|
||||
|
||||
mode = RT3883_PCI_MODE_NONE;
|
||||
for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
|
||||
int devfn;
|
||||
|
||||
if (!child->type ||
|
||||
of_node_cmp(child->type, "pci") != 0)
|
||||
continue;
|
||||
|
||||
devfn = of_pci_get_devfn(child);
|
||||
if (devfn < 0)
|
||||
continue;
|
||||
|
||||
switch (PCI_SLOT(devfn)) {
|
||||
case 1:
|
||||
mode |= RT3883_PCI_MODE_PCIE;
|
||||
break;
|
||||
|
||||
case 17:
|
||||
case 18:
|
||||
mode |= RT3883_PCI_MODE_PCI;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (mode == RT3883_PCI_MODE_NONE) {
|
||||
dev_err(dev, "unable to determine PCI mode\n");
|
||||
err = -EINVAL;
|
||||
goto err_put_hb_node;
|
||||
}
|
||||
|
||||
dev_info(dev, "mode:%s%s\n",
|
||||
(mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
|
||||
(mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
|
||||
|
||||
rt3883_pci_preinit(rpc, mode);
|
||||
|
||||
rpc->pci_controller.pci_ops = &rt3883_pci_ops;
|
||||
rpc->pci_controller.io_resource = &rpc->io_res;
|
||||
rpc->pci_controller.mem_resource = &rpc->mem_res;
|
||||
|
||||
/* Load PCI I/O and memory resources from DT */
|
||||
pci_load_of_ranges(&rpc->pci_controller,
|
||||
rpc->pci_controller.of_node);
|
||||
|
||||
rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
|
||||
rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
|
||||
|
||||
ioport_resource.start = rpc->io_res.start;
|
||||
ioport_resource.end = rpc->io_res.end;
|
||||
|
||||
/* PCI */
|
||||
rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
|
||||
rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
|
||||
rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
|
||||
rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
|
||||
rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
|
||||
|
||||
/* PCIe */
|
||||
rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
|
||||
rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
|
||||
rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
|
||||
rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
|
||||
rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
|
||||
|
||||
err = rt3883_pci_irq_init(dev, rpc);
|
||||
if (err)
|
||||
goto err_put_hb_node;
|
||||
|
||||
/* PCIe */
|
||||
val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
|
||||
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
|
||||
|
||||
/* PCI */
|
||||
val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
|
||||
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
|
||||
|
||||
if (mode == RT3883_PCI_MODE_PCIE) {
|
||||
rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
|
||||
rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
|
||||
|
||||
rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
||||
PCI_BASE_ADDRESS_0,
|
||||
RT3883_MEMORY_BASE);
|
||||
/* flush write */
|
||||
rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
||||
PCI_BASE_ADDRESS_0);
|
||||
} else {
|
||||
rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
||||
PCI_IO_BASE, 0x00000101);
|
||||
}
|
||||
|
||||
register_pci_controller(&rpc->pci_controller);
|
||||
|
||||
return 0;
|
||||
|
||||
err_put_hb_node:
|
||||
of_node_put(rpc->pci_controller.of_node);
|
||||
err_put_intc_node:
|
||||
of_node_put(rpc->intc_of_node);
|
||||
return err;
|
||||
}
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct of_irq dev_irq;
|
||||
int err;
|
||||
int irq;
|
||||
|
||||
err = of_irq_map_pci(dev, &dev_irq);
|
||||
if (err) {
|
||||
pr_err("pci %s: unable to get irq map, err=%d\n",
|
||||
pci_name((struct pci_dev *) dev), err);
|
||||
return 0;
|
||||
}
|
||||
|
||||
irq = irq_create_of_mapping(dev_irq.controller,
|
||||
dev_irq.specifier,
|
||||
dev_irq.size);
|
||||
|
||||
if (irq == 0)
|
||||
pr_crit("pci %s: no irq found for pin %u\n",
|
||||
pci_name((struct pci_dev *) dev), pin);
|
||||
else
|
||||
pr_info("pci %s: using irq %d for pin %u\n",
|
||||
pci_name((struct pci_dev *) dev), irq, pin);
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rt3883_pci_ids[] = {
|
||||
{ .compatible = "ralink,rt3883-pci" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
|
||||
|
||||
static struct platform_driver rt3883_pci_driver = {
|
||||
.probe = rt3883_pci_probe,
|
||||
.driver = {
|
||||
.name = "rt3883-pci",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(rt3883_pci_ids),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rt3883_pci_init(void)
|
||||
{
|
||||
return platform_driver_register(&rt3883_pci_driver);
|
||||
}
|
||||
|
||||
postcore_initcall(rt3883_pci_init);
|
||||
|
|
@ -26,6 +26,7 @@ choice
|
|||
bool "RT3883"
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
select HW_HAS_PCI
|
||||
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
||||
|
|
|
|||
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