[PATCH] ahci: implement NCQ suppport
Implement NCQ support. Original implementation is from Jens Axboe. Signed-off-by: Tejun Heo <htejun@gmail.com>
This commit is contained in:
Tejun Heo
Родитель
a9764c2bb5
Коммит
12fad3f965
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@ -56,9 +56,9 @@ enum {
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AHCI_MAX_SG = 168, /* hardware max is 64K */
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AHCI_DMA_BOUNDARY = 0xffffffff,
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AHCI_USE_CLUSTERING = 0,
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AHCI_MAX_CMDS = 1,
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AHCI_MAX_CMDS = 32,
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AHCI_CMD_SZ = 32,
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AHCI_CMD_SLOT_SZ = 32 * AHCI_CMD_SZ,
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AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
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AHCI_RX_FIS_SZ = 256,
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AHCI_CMD_TBL_CDB = 0x40,
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AHCI_CMD_TBL_HDR_SZ = 0x80,
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@ -218,7 +218,8 @@ static struct scsi_host_template ahci_sht = {
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.change_queue_depth = ata_scsi_change_queue_depth,
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.can_queue = AHCI_MAX_CMDS - 1,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = AHCI_MAX_SG,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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@ -533,12 +534,17 @@ static unsigned int ahci_dev_classify(struct ata_port *ap)
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return ata_dev_classify(&tf);
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}
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static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
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static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
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u32 opts)
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{
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pp->cmd_slot[0].opts = cpu_to_le32(opts);
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pp->cmd_slot[0].status = 0;
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pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
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pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
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dma_addr_t cmd_tbl_dma;
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cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
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pp->cmd_slot[tag].opts = cpu_to_le32(opts);
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pp->cmd_slot[tag].status = 0;
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pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
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pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
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}
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static int ahci_clo(struct ata_port *ap)
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@ -610,7 +616,8 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
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fis = pp->cmd_tbl;
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/* issue the first D2H Register FIS */
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ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
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ahci_fill_cmd_slot(pp, 0,
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cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
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tf.ctl |= ATA_SRST;
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ata_tf_to_fis(&tf, fis, 0);
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@ -629,7 +636,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
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msleep(1);
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/* issue the second D2H Register FIS */
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ahci_fill_cmd_slot(pp, cmd_fis_len);
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ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
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tf.ctl &= ~ATA_SRST;
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ata_tf_to_fis(&tf, fis, 0);
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@ -734,9 +741,8 @@ static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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ata_tf_from_fis(d2h_fis, tf);
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}
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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
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{
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struct ahci_port_priv *pp = qc->ap->private_data;
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struct scatterlist *sg;
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struct ahci_sg *ahci_sg;
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unsigned int n_sg = 0;
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@ -746,7 +752,7 @@ static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
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/*
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* Next, the S/G list.
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*/
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ahci_sg = pp->cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
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ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
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ata_for_each_sg(sg, qc) {
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dma_addr_t addr = sg_dma_address(sg);
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u32 sg_len = sg_dma_len(sg);
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@ -767,6 +773,7 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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struct ata_port *ap = qc->ap;
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struct ahci_port_priv *pp = ap->private_data;
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int is_atapi = is_atapi_taskfile(&qc->tf);
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void *cmd_tbl;
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u32 opts;
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const u32 cmd_fis_len = 5; /* five dwords */
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unsigned int n_elem;
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@ -775,16 +782,17 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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* Fill in command table information. First, the header,
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* a SATA Register - Host to Device command FIS.
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*/
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ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
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cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
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ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
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if (is_atapi) {
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memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
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memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
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qc->dev->cdb_len);
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memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
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memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
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}
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n_elem = 0;
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if (qc->flags & ATA_QCFLAG_DMAMAP)
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n_elem = ahci_fill_sg(qc);
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n_elem = ahci_fill_sg(qc, cmd_tbl);
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/*
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* Fill in command slot information.
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@ -795,7 +803,7 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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if (is_atapi)
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opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
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ahci_fill_cmd_slot(pp, opts);
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ahci_fill_cmd_slot(pp, qc->tag, opts);
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}
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static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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@ -865,8 +873,9 @@ static void ahci_host_intr(struct ata_port *ap)
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{
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void __iomem *mmio = ap->host_set->mmio_base;
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void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
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struct ata_queued_cmd *qc;
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u32 status, ci;
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struct ata_eh_info *ehi = &ap->eh_info;
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u32 status, qc_active;
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int rc;
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status = readl(port_mmio + PORT_IRQ_STAT);
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writel(status, port_mmio + PORT_IRQ_STAT);
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@ -876,16 +885,27 @@ static void ahci_host_intr(struct ata_port *ap)
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return;
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}
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if ((qc = ata_qc_from_tag(ap, ap->active_tag))) {
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ci = readl(port_mmio + PORT_CMD_ISSUE);
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if ((ci & 0x1) == 0) {
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ata_qc_complete(qc);
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return;
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}
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if (ap->sactive)
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qc_active = readl(port_mmio + PORT_SCR_ACT);
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else
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qc_active = readl(port_mmio + PORT_CMD_ISSUE);
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rc = ata_qc_complete_multiple(ap, qc_active, NULL);
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if (rc > 0)
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return;
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if (rc < 0) {
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ehi->err_mask |= AC_ERR_HSM;
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ehi->action |= ATA_EH_SOFTRESET;
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ata_port_freeze(ap);
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return;
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}
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/* hmmm... a spurious interupt */
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/* some devices send D2H reg with I bit set during NCQ command phase */
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if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS)
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return;
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/* ignore interim PIO setup fis interrupts */
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if (ata_tag_valid(ap->active_tag)) {
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struct ata_queued_cmd *qc =
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@ -898,8 +918,8 @@ static void ahci_host_intr(struct ata_port *ap)
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if (ata_ratelimit())
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ata_port_printk(ap, KERN_INFO, "spurious interrupt "
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"(irq_stat 0x%x active_tag %d)\n",
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status, ap->active_tag);
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"(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
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status, ap->active_tag, ap->sactive);
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}
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static void ahci_irq_clear(struct ata_port *ap)
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@ -907,7 +927,7 @@ static void ahci_irq_clear(struct ata_port *ap)
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/* TODO */
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}
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static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
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static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
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{
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struct ata_host_set *host_set = dev_instance;
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struct ahci_host_priv *hpriv;
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@ -965,7 +985,9 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
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struct ata_port *ap = qc->ap;
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void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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writel(1, port_mmio + PORT_CMD_ISSUE);
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if (qc->tf.protocol == ATA_PROT_NCQ)
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writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
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writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
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readl(port_mmio + PORT_CMD_ISSUE); /* flush */
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return 0;
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@ -1262,6 +1284,8 @@ static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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VPRINTK("ENTER\n");
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WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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@ -1329,6 +1353,9 @@ static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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goto err_out_hpriv;
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if (hpriv->cap & HOST_CAP_NCQ)
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probe_ent->host_flags |= ATA_FLAG_NCQ;
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ahci_print_info(probe_ent);
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/* FIXME: check ata_device_add return value */
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