drm/amdgpu: move struct gart_funcs into amdgpu_gmc.h
And rename it to struct gmc_funcs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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770d13b19f
Коммит
132f34e4b5
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@ -333,28 +333,6 @@ struct amdgpu_vm_pte_funcs {
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uint32_t incr, uint64_t flags);
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};
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/* provided by the gmc block */
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struct amdgpu_gart_funcs {
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/* flush the vm tlb via mmio */
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void (*flush_gpu_tlb)(struct amdgpu_device *adev,
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uint32_t vmid);
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/* write pte/pde updates using the cpu */
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int (*set_pte_pde)(struct amdgpu_device *adev,
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void *cpu_pt_addr, /* cpu addr of page table */
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uint32_t gpu_page_idx, /* pte/pde to update */
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uint64_t addr, /* addr to write into pte/pde */
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uint64_t flags); /* access flags */
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/* enable/disable PRT support */
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void (*set_prt)(struct amdgpu_device *adev, bool enable);
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/* set pte flags based per asic */
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uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
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uint32_t flags);
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/* get the pde for a given mc addr */
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void (*get_vm_pde)(struct amdgpu_device *adev, int level,
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u64 *dst, u64 *flags);
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uint32_t (*get_invalidate_req)(unsigned int vmid);
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};
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/* provided by the ih block */
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struct amdgpu_ih_funcs {
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/* ring read/write ptr handling, called from interrupt context */
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@ -1797,13 +1775,13 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
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#define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
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#define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
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#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
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#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
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#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags))
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#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
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#define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
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#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
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#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
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#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
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#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
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#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
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#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
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#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
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#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
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#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
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@ -1775,7 +1775,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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adev->mman.buffer_funcs_ring = NULL;
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adev->vm_manager.vm_pte_funcs = NULL;
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adev->vm_manager.vm_pte_num_rings = 0;
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adev->gart.gart_funcs = NULL;
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adev->gmc.gmc_funcs = NULL;
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adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
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bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
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@ -241,14 +241,14 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
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continue;
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for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
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amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
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amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
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t, page_base, flags);
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page_base += AMDGPU_GPU_PAGE_SIZE;
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}
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}
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mb();
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amdgpu_asic_flush_hdp(adev);
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amdgpu_gart_flush_gpu_tlb(adev, 0);
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amdgpu_gmc_flush_gpu_tlb(adev, 0);
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return 0;
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}
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@ -280,7 +280,7 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
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for (i = 0; i < pages; i++) {
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page_base = dma_addr[i];
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for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
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amdgpu_gart_set_pte_pde(adev, dst, t, page_base, flags);
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amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
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page_base += AMDGPU_GPU_PAGE_SIZE;
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}
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}
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@ -331,7 +331,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
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mb();
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amdgpu_asic_flush_hdp(adev);
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amdgpu_gart_flush_gpu_tlb(adev, 0);
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amdgpu_gmc_flush_gpu_tlb(adev, 0);
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return 0;
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}
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@ -31,7 +31,6 @@
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*/
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struct amdgpu_device;
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struct amdgpu_bo;
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struct amdgpu_gart_funcs;
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#define AMDGPU_GPU_PAGE_SIZE 4096
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#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
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@ -52,8 +51,6 @@ struct amdgpu_gart {
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/* Asic default pte flags */
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uint64_t gart_pte_flags;
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const struct amdgpu_gart_funcs *gart_funcs;
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};
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int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
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@ -634,7 +634,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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if (r)
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goto error_backoff;
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va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
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va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
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r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
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args->offset_in_bo, args->map_size,
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va_flags);
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@ -654,7 +654,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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if (r)
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goto error_backoff;
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va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
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va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
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r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
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args->offset_in_bo, args->map_size,
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va_flags);
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@ -48,6 +48,27 @@ struct amdgpu_vmhub {
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/*
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* GPU MC structures, functions & helpers
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*/
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struct amdgpu_gmc_funcs {
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/* flush the vm tlb via mmio */
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void (*flush_gpu_tlb)(struct amdgpu_device *adev,
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uint32_t vmid);
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/* write pte/pde updates using the cpu */
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int (*set_pte_pde)(struct amdgpu_device *adev,
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void *cpu_pt_addr, /* cpu addr of page table */
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uint32_t gpu_page_idx, /* pte/pde to update */
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uint64_t addr, /* addr to write into pte/pde */
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uint64_t flags); /* access flags */
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/* enable/disable PRT support */
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void (*set_prt)(struct amdgpu_device *adev, bool enable);
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/* set pte flags based per asic */
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uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
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uint32_t flags);
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/* get the pde for a given mc addr */
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void (*get_vm_pde)(struct amdgpu_device *adev, int level,
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u64 *dst, u64 *flags);
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uint32_t (*get_invalidate_req)(unsigned int vmid);
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};
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struct amdgpu_gmc {
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resource_size_t aper_size;
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resource_size_t aper_base;
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@ -79,6 +100,8 @@ struct amdgpu_gmc {
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/* protects concurrent invalidation */
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spinlock_t invalidate_lock;
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bool translate_further;
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const struct amdgpu_gmc_funcs *gmc_funcs;
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};
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#endif
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@ -679,7 +679,7 @@ static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
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value = params->pages_addr ?
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amdgpu_vm_map_gart(params->pages_addr, addr) :
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addr;
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amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
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amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
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i, value, flags);
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addr += incr;
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}
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@ -738,7 +738,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
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level += params->adev->vm_manager.root_level;
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pt = amdgpu_bo_gpu_offset(bo);
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flags = AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(params->adev, level, &pt, &flags);
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amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
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if (shadow) {
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pde = shadow_addr + (entry - parent->entries) * 8;
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params->func(params, pde, pt, 1, 0, flags);
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@ -967,8 +967,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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}
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entry->huge = true;
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amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0,
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&dst, &flags);
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amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
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if (p->func == amdgpu_vm_cpu_set_ptes) {
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pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
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@ -1485,7 +1484,7 @@ static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
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spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
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enable = !!atomic_read(&adev->vm_manager.num_prt_users);
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adev->gart.gart_funcs->set_prt(adev, enable);
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adev->gmc.gmc_funcs->set_prt(adev, enable);
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spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
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}
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@ -1494,7 +1493,7 @@ static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
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*/
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static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
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{
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if (!adev->gart.gart_funcs->set_prt)
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if (!adev->gmc.gmc_funcs->set_prt)
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return;
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if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
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@ -1529,7 +1528,7 @@ static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
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{
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struct amdgpu_prt_cb *cb;
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if (!adev->gart.gart_funcs->set_prt)
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if (!adev->gmc.gmc_funcs->set_prt)
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return;
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cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
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@ -2405,7 +2404,7 @@ static void amdgpu_vm_free_levels(struct amdgpu_device *adev,
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void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
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{
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struct amdgpu_bo_va_mapping *mapping, *tmp;
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bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
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bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
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struct amdgpu_bo *root;
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u64 fault;
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int i, r;
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@ -3688,11 +3688,11 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
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uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
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uint64_t flags = AMDGPU_PTE_VALID;
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unsigned eng = ring->vm_inv_eng;
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amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
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pd_addr |= flags;
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gfx_v9_0_write_data_to_reg(ring, usepfp, true,
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@ -37,7 +37,7 @@
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#include "dce/dce_6_0_sh_mask.h"
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#include "si_enums.h"
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static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
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static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
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static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
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static int gmc_v6_0_wait_for_idle(void *handle);
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@ -357,16 +357,13 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
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return 0;
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}
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static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
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uint32_t vmid)
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static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
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{
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WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
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}
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static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
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void *cpu_pt_addr,
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uint32_t gpu_page_idx,
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uint64_t addr,
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static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
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uint32_t gpu_page_idx, uint64_t addr,
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uint64_t flags)
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{
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void __iomem *ptr = (void *)cpu_pt_addr;
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@ -559,7 +556,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
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else
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gmc_v6_0_set_fault_enable_default(adev, true);
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gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
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gmc_v6_0_flush_gpu_tlb(adev, 0);
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dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
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(unsigned)(adev->gmc.gart_size >> 20),
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(unsigned long long)adev->gart.table_addr);
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@ -793,7 +790,7 @@ static int gmc_v6_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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gmc_v6_0_set_gart_funcs(adev);
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gmc_v6_0_set_gmc_funcs(adev);
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gmc_v6_0_set_irq_funcs(adev);
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return 0;
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@ -1127,9 +1124,9 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
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.set_powergating_state = gmc_v6_0_set_powergating_state,
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};
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static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
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.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
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.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
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static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
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.flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
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.set_pte_pde = gmc_v6_0_set_pte_pde,
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.set_prt = gmc_v6_0_set_prt,
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.get_vm_pde = gmc_v6_0_get_vm_pde,
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.get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
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@ -1140,10 +1137,10 @@ static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
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.process = gmc_v6_0_process_interrupt,
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};
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static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
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static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
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{
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if (adev->gart.gart_funcs == NULL)
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adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
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if (adev->gmc.gmc_funcs == NULL)
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adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
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}
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static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
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@ -43,7 +43,7 @@
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#include "amdgpu_atombios.h"
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static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
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static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
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static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
|
||||
static int gmc_v7_0_wait_for_idle(void *handle);
|
||||
|
||||
|
@ -422,22 +422,21 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
|
|||
*/
|
||||
|
||||
/**
|
||||
* gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
|
||||
* gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @vmid: vm instance to flush
|
||||
*
|
||||
* Flush the TLB for the requested page table (CIK).
|
||||
*/
|
||||
static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
||||
uint32_t vmid)
|
||||
static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
|
||||
{
|
||||
/* bits 0-15 are the VM contexts0-15 */
|
||||
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
|
||||
}
|
||||
|
||||
/**
|
||||
* gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
|
||||
* gmc_v7_0_set_pte_pde - update the page tables using MMIO
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @cpu_pt_addr: cpu address of the page table
|
||||
|
@ -447,10 +446,8 @@ static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
|||
*
|
||||
* Update the page tables using the CPU.
|
||||
*/
|
||||
static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
|
||||
void *cpu_pt_addr,
|
||||
uint32_t gpu_page_idx,
|
||||
uint64_t addr,
|
||||
static int gmc_v7_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
|
||||
uint32_t gpu_page_idx, uint64_t addr,
|
||||
uint64_t flags)
|
||||
{
|
||||
void __iomem *ptr = (void *)cpu_pt_addr;
|
||||
|
@ -672,7 +669,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
|
|||
WREG32(mmCHUB_CONTROL, tmp);
|
||||
}
|
||||
|
||||
gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
|
||||
gmc_v7_0_flush_gpu_tlb(adev, 0);
|
||||
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
||||
(unsigned)(adev->gmc.gart_size >> 20),
|
||||
(unsigned long long)adev->gart.table_addr);
|
||||
|
@ -919,7 +916,7 @@ static int gmc_v7_0_early_init(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
gmc_v7_0_set_gart_funcs(adev);
|
||||
gmc_v7_0_set_gmc_funcs(adev);
|
||||
gmc_v7_0_set_irq_funcs(adev);
|
||||
|
||||
adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
|
||||
|
@ -1306,9 +1303,9 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
|
|||
.set_powergating_state = gmc_v7_0_set_powergating_state,
|
||||
};
|
||||
|
||||
static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
|
||||
.flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
|
||||
.set_pte_pde = gmc_v7_0_gart_set_pte_pde,
|
||||
static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
|
||||
.flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
|
||||
.set_pte_pde = gmc_v7_0_set_pte_pde,
|
||||
.set_prt = gmc_v7_0_set_prt,
|
||||
.get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
|
||||
.get_vm_pde = gmc_v7_0_get_vm_pde
|
||||
|
@ -1319,10 +1316,10 @@ static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
|
|||
.process = gmc_v7_0_process_interrupt,
|
||||
};
|
||||
|
||||
static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
|
||||
static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
if (adev->gart.gart_funcs == NULL)
|
||||
adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
|
||||
if (adev->gmc.gmc_funcs == NULL)
|
||||
adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
|
||||
}
|
||||
|
||||
static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
|
||||
|
|
|
@ -45,7 +45,7 @@
|
|||
#include "amdgpu_atombios.h"
|
||||
|
||||
|
||||
static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
|
||||
static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
|
||||
static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
|
||||
static int gmc_v8_0_wait_for_idle(void *handle);
|
||||
|
||||
|
@ -597,14 +597,14 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
|
|||
*/
|
||||
|
||||
/**
|
||||
* gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
|
||||
* gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @vmid: vm instance to flush
|
||||
*
|
||||
* Flush the TLB for the requested page table (CIK).
|
||||
*/
|
||||
static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
||||
static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
|
||||
uint32_t vmid)
|
||||
{
|
||||
/* bits 0-15 are the VM contexts0-15 */
|
||||
|
@ -612,7 +612,7 @@ static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
|||
}
|
||||
|
||||
/**
|
||||
* gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
|
||||
* gmc_v8_0_set_pte_pde - update the page tables using MMIO
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @cpu_pt_addr: cpu address of the page table
|
||||
|
@ -622,10 +622,8 @@ static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
|||
*
|
||||
* Update the page tables using the CPU.
|
||||
*/
|
||||
static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
|
||||
void *cpu_pt_addr,
|
||||
uint32_t gpu_page_idx,
|
||||
uint64_t addr,
|
||||
static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
|
||||
uint32_t gpu_page_idx, uint64_t addr,
|
||||
uint64_t flags)
|
||||
{
|
||||
void __iomem *ptr = (void *)cpu_pt_addr;
|
||||
|
@ -888,7 +886,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
|
|||
else
|
||||
gmc_v8_0_set_fault_enable_default(adev, true);
|
||||
|
||||
gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
|
||||
gmc_v8_0_flush_gpu_tlb(adev, 0);
|
||||
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
||||
(unsigned)(adev->gmc.gart_size >> 20),
|
||||
(unsigned long long)adev->gart.table_addr);
|
||||
|
@ -1009,7 +1007,7 @@ static int gmc_v8_0_early_init(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
gmc_v8_0_set_gart_funcs(adev);
|
||||
gmc_v8_0_set_gmc_funcs(adev);
|
||||
gmc_v8_0_set_irq_funcs(adev);
|
||||
|
||||
adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
|
||||
|
@ -1640,9 +1638,9 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
|
|||
.get_clockgating_state = gmc_v8_0_get_clockgating_state,
|
||||
};
|
||||
|
||||
static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
|
||||
.flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
|
||||
.set_pte_pde = gmc_v8_0_gart_set_pte_pde,
|
||||
static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
|
||||
.flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
|
||||
.set_pte_pde = gmc_v8_0_set_pte_pde,
|
||||
.set_prt = gmc_v8_0_set_prt,
|
||||
.get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
|
||||
.get_vm_pde = gmc_v8_0_get_vm_pde
|
||||
|
@ -1653,10 +1651,10 @@ static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
|
|||
.process = gmc_v8_0_process_interrupt,
|
||||
};
|
||||
|
||||
static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
|
||||
static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
if (adev->gart.gart_funcs == NULL)
|
||||
adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
|
||||
if (adev->gmc.gmc_funcs == NULL)
|
||||
adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
|
||||
}
|
||||
|
||||
static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
|
||||
|
|
|
@ -316,14 +316,14 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
|
|||
*/
|
||||
|
||||
/**
|
||||
* gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
|
||||
* gmc_v9_0_flush_gpu_tlb - gart tlb flush callback
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @vmid: vm instance to flush
|
||||
*
|
||||
* Flush the TLB for the requested page table.
|
||||
*/
|
||||
static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
||||
static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
|
||||
uint32_t vmid)
|
||||
{
|
||||
/* Use register 17 for GART */
|
||||
|
@ -367,7 +367,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
|||
}
|
||||
|
||||
/**
|
||||
* gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
|
||||
* gmc_v9_0_set_pte_pde - update the page tables using MMIO
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @cpu_pt_addr: cpu address of the page table
|
||||
|
@ -377,10 +377,8 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
|
|||
*
|
||||
* Update the page tables using the CPU.
|
||||
*/
|
||||
static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
|
||||
void *cpu_pt_addr,
|
||||
uint32_t gpu_page_idx,
|
||||
uint64_t addr,
|
||||
static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
|
||||
uint32_t gpu_page_idx, uint64_t addr,
|
||||
uint64_t flags)
|
||||
{
|
||||
void __iomem *ptr = (void *)cpu_pt_addr;
|
||||
|
@ -491,25 +489,25 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
|
|||
}
|
||||
}
|
||||
|
||||
static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
|
||||
.flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
|
||||
.set_pte_pde = gmc_v9_0_gart_set_pte_pde,
|
||||
static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
|
||||
.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
|
||||
.set_pte_pde = gmc_v9_0_set_pte_pde,
|
||||
.get_invalidate_req = gmc_v9_0_get_invalidate_req,
|
||||
.get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
|
||||
.get_vm_pde = gmc_v9_0_get_vm_pde
|
||||
};
|
||||
|
||||
static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
|
||||
static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
if (adev->gart.gart_funcs == NULL)
|
||||
adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
|
||||
if (adev->gmc.gmc_funcs == NULL)
|
||||
adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
|
||||
}
|
||||
|
||||
static int gmc_v9_0_early_init(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
gmc_v9_0_set_gart_funcs(adev);
|
||||
gmc_v9_0_set_gmc_funcs(adev);
|
||||
gmc_v9_0_set_irq_funcs(adev);
|
||||
|
||||
adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
|
||||
|
@ -981,7 +979,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
gfxhub_v1_0_set_fault_enable_default(adev, value);
|
||||
mmhub_v1_0_set_fault_enable_default(adev, value);
|
||||
gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
|
||||
gmc_v9_0_flush_gpu_tlb(adev, 0);
|
||||
|
||||
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
||||
(unsigned)(adev->gmc.gart_size >> 20),
|
||||
|
|
|
@ -1136,11 +1136,11 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned vmid, uint64_t pd_addr)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
|
||||
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
|
||||
uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
|
||||
uint64_t flags = AMDGPU_PTE_VALID;
|
||||
unsigned eng = ring->vm_inv_eng;
|
||||
|
||||
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
pd_addr |= flags;
|
||||
|
||||
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
|
||||
|
|
|
@ -1294,12 +1294,12 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned vmid, uint64_t pd_addr)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
|
||||
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
|
||||
uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
|
||||
uint64_t flags = AMDGPU_PTE_VALID;
|
||||
unsigned eng = ring->vm_inv_eng;
|
||||
uint32_t data0, data1, mask;
|
||||
|
||||
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
pd_addr |= flags;
|
||||
|
||||
data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
|
||||
|
@ -1346,11 +1346,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned int vmid, uint64_t pd_addr)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
|
||||
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
|
||||
uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
|
||||
uint64_t flags = AMDGPU_PTE_VALID;
|
||||
unsigned eng = ring->vm_inv_eng;
|
||||
|
||||
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
pd_addr |= flags;
|
||||
|
||||
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
|
||||
|
|
|
@ -968,11 +968,11 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned int vmid, uint64_t pd_addr)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
|
||||
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
|
||||
uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
|
||||
uint64_t flags = AMDGPU_PTE_VALID;
|
||||
unsigned eng = ring->vm_inv_eng;
|
||||
|
||||
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
pd_addr |= flags;
|
||||
|
||||
amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
|
||||
|
|
|
@ -891,12 +891,12 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned vmid, uint64_t pd_addr)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
|
||||
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
|
||||
uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
|
||||
uint64_t flags = AMDGPU_PTE_VALID;
|
||||
unsigned eng = ring->vm_inv_eng;
|
||||
uint32_t data0, data1, mask;
|
||||
|
||||
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
pd_addr |= flags;
|
||||
|
||||
data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
|
||||
|
@ -1024,11 +1024,11 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
|
|||
unsigned int vmid, uint64_t pd_addr)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
|
||||
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
|
||||
uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
|
||||
uint64_t flags = AMDGPU_PTE_VALID;
|
||||
unsigned eng = ring->vm_inv_eng;
|
||||
|
||||
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
|
||||
pd_addr |= flags;
|
||||
|
||||
amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
|
||||
|
|
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Ссылка в новой задаче