dt-bindings: pci: tegra: Update for per-lane PHYs
The XUSB pad controller allows PCIe lanes to be controlled individually, providing fine-grained control over their power state. Previous attempts at describing the XUSB pad controller in DT had erroneously assumed that all PCIe lanes were driven by the same PHY, and hence the PCI host controller would reference only a single PHY. Moving to a representation of per-lane PHYs requires that the operating system driver for the PCI host controller have access to the set of PHY devices that make up the connection of each root port in order to power up and down all of the lanes as necessary. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding
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@ -60,11 +60,14 @@ Required properties:
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- afi
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- pcie_x
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Required properties on Tegra124 and later:
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Required properties on Tegra124 and later (deprecated):
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- phys: Must contain an entry for each entry in phy-names.
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- phy-names: Must include the following entries:
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- pcie
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These properties are deprecated in favour of per-lane PHYs define in each of
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the root ports (see below).
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Power supplies for Tegra20:
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- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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@ -122,11 +125,22 @@ Required properties:
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- Root port 0 uses 4 lanes, root port 1 is unused.
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- Both root ports use 2 lanes.
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Example:
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Required properties for Tegra124 and later:
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane. Note that the number
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of entries does not have to (though usually will) be equal to the specified
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number of lanes in the nvidia,num-lanes property. Entries are of the form
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"pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
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Examples:
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=========
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Tegra20:
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--------
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SoC DTSI:
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pcie-controller {
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pcie-controller@80003000 {
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compatible = "nvidia,tegra20-pcie";
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device_type = "pci";
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reg = <0x80003000 0x00000800 /* PADS registers */
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@ -186,10 +200,9 @@ SoC DTSI:
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};
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};
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Board DTS:
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pcie-controller {
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pcie-controller@80003000 {
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status = "okay";
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vdd-supply = <&pci_vdd_reg>;
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@ -222,3 +235,204 @@ if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
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device nodes need to be added in order to allow the bus' children to be
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instantiated at the proper location in the operating system's device tree (as
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illustrated by the optional nodes in the example above).
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Tegra30:
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--------
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SoC DTSI:
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pcie-controller@00003000 {
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compatible = "nvidia,tegra30-pcie";
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device_type = "pci";
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reg = <0x00003000 0x00000800 /* PADS registers */
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0x00003800 0x00000200 /* AFI registers */
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0x10000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
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GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
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0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
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clocks = <&tegra_car TEGRA30_CLK_PCIE>,
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<&tegra_car TEGRA30_CLK_AFI>,
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<&tegra_car TEGRA30_CLK_PLL_E>,
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<&tegra_car TEGRA30_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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};
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Board DTS:
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pcie-controller@00003000 {
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status = "okay";
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avdd-pexa-supply = <&ldo1_reg>;
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vdd-pexa-supply = <&ldo1_reg>;
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avdd-pexb-supply = <&ldo1_reg>;
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vdd-pexb-supply = <&ldo1_reg>;
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avdd-pex-pll-supply = <&ldo1_reg>;
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avdd-plle-supply = <&ldo1_reg>;
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vddio-pex-ctl-supply = <&sys_3v3_reg>;
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hvdd-pex-supply = <&sys_3v3_pexs_reg>;
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pci@1,0 {
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status = "okay";
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};
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pci@3,0 {
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status = "okay";
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};
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};
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Tegra124:
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---------
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SoC DTSI:
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pcie-controller@01003000 {
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compatible = "nvidia,tegra124-pcie";
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device_type = "pci";
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reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
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0x0 0x01003800 0x0 0x00000800 /* AFI registers */
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0x0 0x02000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
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0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
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0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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clocks = <&tegra_car TEGRA124_CLK_PCIE>,
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<&tegra_car TEGRA124_CLK_AFI>,
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<&tegra_car TEGRA124_CLK_PLL_E>,
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<&tegra_car TEGRA124_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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Board DTS:
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pcie-controller@01003000 {
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status = "okay";
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avddio-pex-supply = <&vdd_1v05_run>;
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dvddio-pex-supply = <&vdd_1v05_run>;
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avdd-pex-pll-supply = <&vdd_1v05_run>;
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hvdd-pex-supply = <&vdd_3v3_lp0>;
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hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
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vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
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avdd-pll-erefe-supply = <&avdd_1v05_run>;
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/* Mini PCIe */
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pci@1,0 {
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
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phy-names = "pcie-0";
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status = "okay";
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};
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/* Gigabit Ethernet */
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pci@2,0 {
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
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phy-names = "pcie-0";
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status = "okay";
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};
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};
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