clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
This patchset adds DT support for all the AXI, AHB, APB0 and APB1 gates present on sunxi SoCs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Emilio López
Mike Turquette
Родитель
056b205316
Коммит
13569a709a
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@ -10,15 +10,23 @@ Required properties:
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"allwinner,sun4i-pll1-clk" - for the main PLL clock
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"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-axi-clk" - for the AXI clock
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"allwinner,sun4i-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-ahb-clk" - for the AHB clock
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"allwinner,sun4i-ahb-gates-clk" - for the AHB gates
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"allwinner,sun4i-apb0-clk" - for the APB0 clock
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"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
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"allwinner,sun4i-apb1-clk" - for the APB1 clock
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"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
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"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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- clocks : shall be the input parent clock(s) phandle for the clock
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- #clock-cells : from common clock binding; shall be set to 0.
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- #clock-cells : from common clock binding; shall be set to 0 except for
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"allwinner,sun4i-*-gates-clk" where it shall be set to 1
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Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
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- clock-output-names : the corresponding gate names that the clock controls
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For example:
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@ -42,3 +50,102 @@ cpu: cpu@01c20054 {
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>;
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};
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Gate clock outputs
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The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
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their corresponding offsets as present on sun4i are listed below. Note that
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some of these gates are not present on sun5i.
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* AXI gates ("allwinner,sun4i-axi-gates-clk")
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DRAM 0
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* AHB gates ("allwinner,sun4i-ahb-gates-clk")
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USB0 0
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EHCI0 1
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OHCI0 2*
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EHCI1 3
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OHCI1 4*
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SS 5
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DMA 6
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BIST 7
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MMC0 8
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MMC1 9
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MMC2 10
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MMC3 11
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MS 12**
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NAND 13
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SDRAM 14
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ACE 16
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EMAC 17
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TS 18
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SPI0 20
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SPI1 21
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SPI2 22
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SPI3 23
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PATA 24
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SATA 25**
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GPS 26*
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VE 32
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TVD 33
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TVE0 34
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TVE1 35
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LCD0 36
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LCD1 37
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CSI0 40
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CSI1 41
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HDMI 43
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DE_BE0 44
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DE_BE1 45
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DE_FE0 46
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DE_FE1 47
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MP 50
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MALI400 52
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* APB0 gates ("allwinner,sun4i-apb0-gates-clk")
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CODEC 0
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SPDIF 1*
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AC97 2
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IIS 3
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PIO 5
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IR0 6
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IR1 7
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KEYPAD 10
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* APB1 gates ("allwinner,sun4i-apb1-gates-clk")
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I2C0 0
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I2C1 1
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I2C2 2
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CAN 4
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SCR 5
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PS20 6
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PS21 7
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UART0 16
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UART1 17
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UART2 18
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UART3 19
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UART4 20
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UART5 21
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UART6 22
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UART7 23
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Notation:
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[*]: The datasheet didn't mention these, but they are present on AW code
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[**]: The datasheet had this marked as "NC" but they are used on AW code
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@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
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}
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/**
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* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
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*/
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#define SUNXI_GATES_MAX_SIZE 64
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struct gates_data {
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DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
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};
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static const __initconst struct gates_data axi_gates_data = {
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.mask = {1},
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};
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static const __initconst struct gates_data ahb_gates_data = {
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.mask = {0x7F77FFF, 0x14FB3F},
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};
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static const __initconst struct gates_data apb0_gates_data = {
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.mask = {0x4EF},
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};
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static const __initconst struct gates_data apb1_gates_data = {
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.mask = {0xFF00F7},
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};
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static void __init sunxi_gates_clk_setup(struct device_node *node,
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struct gates_data *data)
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{
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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void *reg;
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int qty;
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int i = 0;
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int j = 0;
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int ignore;
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reg = of_iomap(node, 0);
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clk_parent = of_clk_get_parent_name(node, 0);
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/* Worst-case size approximation and memory allocation */
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qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
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clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data)
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return;
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clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks) {
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kfree(clk_data);
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return;
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}
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for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
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of_property_read_string_index(node, "clock-output-names",
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j, &clk_name);
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/* No driver claims this clock, but it should remain gated */
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ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
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clk_data->clks[i] = clk_register_gate(NULL, clk_name,
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clk_parent, ignore,
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reg + 4 * (i/32), i % 32,
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0, &clk_lock);
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WARN_ON(IS_ERR(clk_data->clks[i]));
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j++;
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}
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/* Adjust to the real max */
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clk_data->clk_num = i;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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/* Matches for of_clk_init */
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static const __initconst struct of_device_id clk_match[] = {
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{.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
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@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
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{}
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};
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/* Matches for gate clocks */
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static const __initconst struct of_device_id clk_gates_match[] = {
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{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
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{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
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{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
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{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
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{}
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};
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static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
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void *function)
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{
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@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
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/* Register mux clocks */
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of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
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/* Register gate clocks */
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of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
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}
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