PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
[ Upstream commit 86f271f22bbb6391410a07e08d6ca3757fda01fa ] Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf Link: https://lore.kernel.org/linux-pci/16e1fcae-1ea7-46be-b157-096e05661b15@siemens.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Achal Verma <a-verma1@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -35,6 +35,11 @@
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#define PCIE_DEVICEID_SHIFT 16
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/* Application registers */
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#define PID 0x000
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#define RTL GENMASK(15, 11)
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#define RTL_SHIFT 11
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#define AM6_PCI_PG1_RTL_VER 0x15
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#define CMD_STATUS 0x004
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#define LTSSM_EN_VAL BIT(0)
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#define OB_XLAT_EN_VAL BIT(1)
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@ -105,6 +110,8 @@
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#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
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#define PCI_DEVICE_ID_TI_AM654X 0xb00c
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struct ks_pcie_of_data {
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enum dw_pcie_device_mode mode;
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const struct dw_pcie_host_ops *host_ops;
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@ -528,7 +535,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci)
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static void ks_pcie_quirk(struct pci_dev *dev)
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{
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struct pci_bus *bus = dev->bus;
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struct keystone_pcie *ks_pcie;
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struct device *bridge_dev;
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struct pci_dev *bridge;
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u32 val;
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static const struct pci_device_id rc_pci_devids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
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.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
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@ -540,6 +551,11 @@ static void ks_pcie_quirk(struct pci_dev *dev)
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.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
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{ 0, },
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};
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static const struct pci_device_id am6_pci_devids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X),
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.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
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{ 0, },
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};
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if (pci_is_root_bus(bus))
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bridge = dev;
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@ -561,10 +577,36 @@ static void ks_pcie_quirk(struct pci_dev *dev)
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*/
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if (pci_match_id(rc_pci_devids, bridge)) {
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if (pcie_get_readrq(dev) > 256) {
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dev_info(&dev->dev, "limiting MRRS to 256\n");
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dev_info(&dev->dev, "limiting MRRS to 256 bytes\n");
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pcie_set_readrq(dev, 256);
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}
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}
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/*
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* Memory transactions fail with PCI controller in AM654 PG1.0
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* when MRRS is set to more than 128 bytes. Force the MRRS to
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* 128 bytes in all downstream devices.
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*/
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if (pci_match_id(am6_pci_devids, bridge)) {
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bridge_dev = pci_get_host_bridge_device(dev);
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if (!bridge_dev && !bridge_dev->parent)
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return;
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ks_pcie = dev_get_drvdata(bridge_dev->parent);
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if (!ks_pcie)
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return;
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val = ks_pcie_app_readl(ks_pcie, PID);
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val &= RTL;
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val >>= RTL_SHIFT;
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if (val != AM6_PCI_PG1_RTL_VER)
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return;
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if (pcie_get_readrq(dev) > 128) {
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dev_info(&dev->dev, "limiting MRRS to 128 bytes\n");
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pcie_set_readrq(dev, 128);
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}
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}
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
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